Feb 14, 2011

Is SPICE good enough for tomorrow's analog?

by Nagel, L.W.; McAndrew, C.C.;
IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM 2010),
Digital Object Identifier: 10.1109/BIPOL.2010.5668096
Publication Year: 2010 , Page(s): 106 - 112

"The answer to the question posed in the title is an emphatic yes! Because SPICE is fairly general purpose and is not tied to any particular technology (not even only semiconductors), SPICE will play a significant role in the design of integrated circuits for a long time. SPICE will not be used to simulate billion transistor circuits, of course, but instead it will play a key role in developing the devices, device models, building blocks, and behavioral models for the building blocks for the billion transistor chips. SPICE will continue to play the role of the foundation of the integrated circuit design infrastructure." [Nagel, L.W.; McAndrew, C.C.]

Feb 7, 2011

[mos-ak] C4P MOS-AK/GSA Workshop at UPMC/LIP6 Paris on 7-8 April 2011

C4P MOS-AK/GSA Workshop at UPMC/LIP6 Paris on 7-8 April 2011
http://www.mos-ak.org/paris/

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
UPMC/LIP6 Paris on 7-8 April 2011

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
Authors are asked to submit a short (~200words) abstract using on-line
submission form by MARCH.1st:
http://www.mos-ak.org/paris/abstracts.php

Intending authors should also note the following deadlines:
* Call for Papers - Feb.2011
* Notification of preliminary acceptance - March 2011
* Final Workshop Program - end of March 2011
* MOS-AK/GSA Workshop - 7-8 April 2011

Further details and updates http://www.mos-ak.org/paris/
On-line
workshop registration http://www.mos-ak.org/paris/registration.php

Local Organizing Committee:
Marie-Minerve Louerat, UPMC/LIP6
Ramy Iskander, UPMC/LIP6

Technical Program Committee:
Marie-Minerve Louerat, UPMC/LIP6
Andrei Vladimirescu, ISEP/UCB
Costin Anghel, ISEP
Ramy Iskander, UPMC/LIP6

Extended MOS-AK/GSA Committee:
Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA)
Chelsea Boone, GSA; Director of Research
Kayal Rajendran, GSA; Senior Research Analyst
Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager
MOS-AK/GSA North America:
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Roberto Tinti, Agilent EEsof Division
MOS-AK/GSA South America:
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil
Sergio Bampi, UFRGS, Brazil
Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK/GSA Europe:
Chair: Ehrenfried Seebacher, austriamicrosystems AG
Co-Chair: Alexander Petr, XFab
Co-Chair: Prof. Benjamin Iniguez, URV
James Victory, Sentinel-IC
MOS-AK/GSA Asia/Pacific:
Chair: Goichi Yokomizo, STARC, Japan
Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan
Co-Chair: Xing Zhou, NTU, Singapore
A.B. Bhattacharyya, JIIT, India

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IEEE SCV EDS: February 8 Photovoltaic Technology Talk

Talk on photovoltaic technology on Feb. 8th. Module reliability is a key issue in photovoltaic technology.

Feb 8th:
Dr. Glenn Alers – UC Santa Cruz,
“Photovoltaic Module Reliability and Failure Analysis: Enduring a storm”

(Next month event) March 1st:
Dr. Geert Vandenberghe, IMEC,
“Lithography Options for 22nm and Beyond”

More information at the IEEE Santa Clara Valley EDS Chapter Home Page
http://www.ewh.ieee.org/r6/scv/eds/