Papers in SSE (vol 56, issue 1, february 2011)

Temperature model for Ge₂Sb₂Te₅ phase change memory in electrical memory device   Original Research Article

Pages 13-17
Daolin Cai, Zhitang Song, Houpeng Chen, Xiaogang Chen

Research highlights

► Temperature model is constituted by an active region and a dispersed-heat region. ► Calculated and simulated the radius and crystalline fraction. ► Crystalline fraction and temperature increase with the reset voltage increasing.


 Microwave noise modeling of FinFETs   Original Research Article

Pages 18-22
Giovanni Crupi, Alina Caddemi, Dominique M.M.-P. Schreurs, Wojciech Wiatr, Abdelkarim Mercha


 Comprehensive numerical simulation of threshold-voltage transients in nitride memories   Original Research Article

Pages 23-30
Aurelio Mauri, Salvatore M. Amoroso, Christian Monzio Compagnoni, Alessandro Maconi, Alessandro S. Spinelli

Research highlights

► We present a complete model to describe charge trap devices behavior. ► In this study any mathematical aspect regarding holes and electrons is detailed modeled. ► Experimental data coming from different TANOS and SONOS devices are correctly reproduced.


 A unified short-channel compact model for cylindrical surrounding-gate MOSFET   Original Research Article

Pages 40-46
Bastien Cousin, Marina Reyboz, Olivier Rozeau, Marie-Anne Jaud, Thomas Ernst, Jalal Jomaah

Research highlights

► A compact model of short-channel effects for GAA MOSFET has been developed. ► The model uses a well-known extraction method making the model simple and accurate. ► Each term is used in a model core in order to provide a short-channel correction. ► The compact model is well described and is suitable with circuit design tools. ► The model is validated using TCAD simulations for all gate lengths down to 10nm.



Physical limitations of the diffusive approximation in semiconductor device modeling   Original Research Article

Pages 60-67
Tigran T. Mnatsakanov, Alexey G. Tandoev, Michael E. Levinshtein, Sergey N. Yurkov

Research highlights

► New criteria for occurrence of the diffusion mode were formulated. ► The applicability limits of the diffusion approximation in simulation were found. ► The analytical results are confirmed by a numerical experiment.


 Direct determination of threshold condition in DG-MOSFETs from the g_m/I_D curve   Original Research Article

Pages 89-94
Ana Isabela Araújo Cunha, Marcelo Antonio Pavanello, Renan Doria Trevisoli, Carlos Galup-Montoro, Marcio Cherem Schneider


Dynamic model of AlGaN/GaN HFET for high voltage switching   Original Research Article

Pages 135-140
Alexei Koudymov



A surface potential based drain current model for asymmetric double gate MOSFETs   Original Research Article

Pages 148-154
Pradipta Dutta, Binit Syamal, N. Mohankumar, C.K. Sarkar

Research highlights

► We model a surface potential based drain current for asymmetric DG MOSFETs. ► The model is applicable for both heavily and lightly doped Silicon channel. ► The surface potential at both the gates are solved using proper Iterative techniques. ► The effect of volume inversion is shown in case of lightly doped channel.



 AlGaN/GaN hybrid MOS-HEMT analytical mobility model   Original Research Article

Pages 201-206
A. Pérez-Tomás, A. Fontserè

Research highlights

► The hybrid normally-off switch AlGaN/GaN MOS-HEMT combines two main advantages: ► The MOS gate control and the high 2DEG mobility in AlGaN/GaN drift region. ► Here, we present simple analytical modeling of the on-resistance of a hybrid MOS-HEMT. ► We investigate the layout, the MOS channel mobility, the effect of a high-k and the temperature. ► The model can aid to understand the device physics and is compatible with TCAD simulation packages.



Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction   

Pages 214-218
J.C. Tinoco, A.G. Martinez-Lopez, J.-P. Raskin

[uSG] New Website

Microelectronics Students' Group website is finished and can be visited at: http://usgroup.eu where you can also find out more about usgroup, as well as their projects and activities. You can also follow usgroup on Twitter and on Facebook. For further information please contact:

Daniel Oliveira (Microelectronics Students' Group)
Faculdade de Engenharia da Universidade do Porto
Rua Dr. Roberto Frias, s/n 4200-465 Porto PORTUGAL

mail: cmos@fe.up.pt, web: cmos.fe.up.pt

[mos-ak] 8th IWCM; Jan.25, 2011; Pacifico Yokohama, Japan

8th International Workshop on Compact Modeling
http://www.aspdac.com/aspdac2011/colocated_event/
January 25(Tue), 2011
Pacifico Yokohama room 419, Yokohama, Japan

The workshop provides an opportunity for the discussion and the
presentation of advances in modeling and simulation of integrated
circuits. Following IWCM sessions are foreseen:

Workshop Opening: M. Miura-Mattausch (chair)
Simulation Methodology (Chair: Z. Yu)
Conventional MOSFET (Chair: G. Yokomizo)
Organic Materials (Chair: W. Grabinski)
Power Device (Chair: Y. J. Park)
Closing: J. He (co-chair)

Complete IWCM program is available on-line:
http://home.hiroshima-u.ac.jp/usdl/IWCM/FILES/IWCM_Program_11_revised.pdf

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[mos-ak] MOS-AK/GSA San Francisco Workshop Press Release

Press release:
MOS-AK/GSA Modeling Working Group Holds Workshop in San Francisco
Experts Share Insight on Electron Device Modeling with Emphasis on
Simulation-Aware Models
can be found on the GSA site at: http://www.gsaglobal.org/news/article.asp?article=2011/0110

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Opprtunity with MNC Product Company in Bangalore

I copy a post from LinkedIn:

Position Description
The member of technical staff (MTS) in this role will be responsible for the implementing and maintaining all device models for the company’s Analog FastSPICE (AFS) circuit simulator. The MTS will also debug various model-related circuit simulation issues such as convergence and accuracy issues, which will require working closely with circuit simulation developers and application engineers. The successful candidate will have sufficient circuit and circuit simulator background for these responsibilities.

Responsibilities

Implement and maintain all device models for the AFS circuit simulator.
Improve performance, convergence, and similar issues related to device models.
Verify device model accuracy and create testcases to validate and regression test accuracy.
Develop and maintain interfaces to implement models from Verilog-A and other simulators.
Lead AFS circuit simulator qualification for various foundry process technologies.
Work with applications and customers on select model and model interface development.
Requirements

3+ years experience in areas related to model development and circuit simulation.
Excellent knowledge of circuits containing diode, bipolar, and MOS devices.
Experience in debugging customer test cases for model and model related issues.
Good knowledge of Verilog-A and modeling in Verilog-A.
Outstanding programming skills in C/C++.
Excellent oral and written communication skills.
Ability work effectively within a worldwide development organization.
Masters or PhD degree in electrical engineering or relevant area.
Desirable

Familiarity with architecture of model implementation in true SPICE accurate simulators.
Previous experience in implementing device models in a circuit simulator.

Interested folks can contact bibin.sundaran at careernet.co.in, 9611833167