Variations in Analog Design

I've just seen a press release in EDN about a new tool for analysis of the impact of parametric variations on the performance of circuits, specially oriented to analog design. This new tool from Solido Design Automation seems a quite potent toolbox, very related to what you can do with UTMOST, but more oriented to integration in a simulation environment. This tool promises to be able to determine the best corners from foundry data, run sensitivity analysis, etc....

If anybody has tested it, I'd like to read first-hand opinions....

Rising salaries in technological sector in 2009?

This is not a post closely related to compact modeling, but I feel that it is relevant... I've read an article in EDN, and it seems that the technological sector is a nice one to be during this crisis. In fact, they say that the unemployment ratio is halt that of the general population, and that salaries are actually growing... Incredible, isn't it? Maybe they hint at a possible explanation, because it seems that most of the people are trying to improve their situation, and that can lead to an increase of the mean salary, since the employers must keep the better...

Anyway, the full article is here... What do you think?

1/f noise in (100) and (110) Si

I've been looking to a paper from the January Issue of J. Vac. Sci. Technol. B, by Philippe Gaubert, Akinobu Teramoto, Weitao Cheng, Tatsufumi Hamada, and Tadahiro Ohmi, "Different mechanism to explain the 1/f noise in n- and p-SOI-MOS transistors fabricated on (110) and (100) silicon-oriented wafers".

They discuss the differences in both orientacions, and present some nice experimental results, with some theory explaining the differences. If you're interested in noise (other than pub music, I mean), perhaps this can interest you.

10.000 visits!!!

We've just got 10.000 visits, which is not too bad considering the quite restricted audience....

Thank you very much for your support!!!



PS: here you have a map showing where the visitors (that's you...) came from today...

2009 Spring MOS-AK Meeting

--- Spring MOS-AK Meeting
--- April 2-3 2008 at IHP GmbH in Frankfurt (Oder)
--- 1st announcement

On behalf of the MOS-AK Organizing Committee, I would like to invite you to the MOS-AK Meeting to be held on April 2-3 at IHP in Frankfurt (Oder). Frankfurt (Oder) and, in particular, the IHP is the place where many electronics systems and semiconductor devices are designed and manufactured. The IHP has a large community of academic researchers and industrial practitioners who are eager to interact with the compact modeling world and EDA community. Moreover, thru it border location, the IHP bridges broad range of HiTech activities between Europe West and East.

The MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the
main theme - compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed- Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers.

The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a poster session is foreseen. The meeting program will be available soon at: http://www.mos-ak.org

--- Tentative Agenda
--------------------
--- APRIL.2:
 * COMON Project Meeting (morning)
 * IHP tutorials and fab visit (afternoon)
 * MOS-AK Networking Reception (evening)

--- APRIL.3:
 * MOS-AK Meeting (all day)
 * two session and poster briefing

--- Important dates:
--------------------
 * 2nd MOS-AK announcement - Feb.21
 * Final workshop program  - March.21
 * MOS-AK Workshop         - April 2-3

Further information including recommended hotels and driving directions will be posted at our web site, soon; please visit regularly: http://www.mos-ak.org

--- Organizing Committee:
 * Prof. Tillack Bernd, IHP; Meeting Chair
 * Prof. Benjamin Iniguez Technical Program Chair
 * Dr. Rene Scholz, IHP; Technical Program Chair
 * Richter Christine, IHP; Executive Assistant
 * Wladek Grabinski, GMC Suisse; Workshop Manager

A post in EDN: Simulation gets speed, capacity boost

A nice article to read. It's not very technical, but interesting anyway (may because of its not-technicallity...). I copy a paragraph:

"Spice remains only part of the simulation picture as designers add RF/wireless-communications capability to an increasing array of products. And even products that offer no RF/wireless features are exhibiting RF performance as process geometries shrink, digital speeds increase, and high-speed serial-I/O ports proliferate. Furthermore, in many cases, as frequencies rise and designers squeeze more functions into smaller and smaller spaces, chip and board design cannot occur in isolation; co-design and simulation of chip, chip package, and board must take place."

If you wish to read more (which I recommend), follow the link to EDN.

Papers in Solid-State Electronics

Many interesting papers in the Jan-09 issue of Solid-State Electronics:

Surface potential equation for bulk MOSFET, by G. Gildenblat, Z. Zhu, and C.C. McAndrew... (Don't miss this one... it's short, but interesting, mainly for starters)

PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations, by W. Wu, X. Li, G. Gildenblat, G.O. Workman, S. Veeraraghavan, C.C. McAndrew, R. van Langevelde, G.D.J. Smit, A.J. Scholten, D.B.M. Klaassen and J. Watts... this is another must, since it's the presentation in society of the latests efforts in SOI modelling of the PSP team!

Modeling short-channel effects in channel thermal noise and induced-gate noise in MOSFETs in the NQS regime, by Sunil Vallur and R.P. Jindal

A charge-based compact model for predicting the current–voltage and capacitance–voltage characteristics of heavily doped cylindrical surrounding-gate MOSFETs, by Feilong Liu, Jian Zhang, Frank He, Feng Liu, Lining Zhang, and Mansun Chan

Analytic resolution of Poisson–Boltzmann equation in nanometric semiconductor junctions, by Hugues Murray... another must, with well explained mathematics...