Well, it seems we're in a boom... I post another one taken from LindekIn:
Requirement:
This work involves theoretical understanding of quantum effects in 22 nm scale devices; these include carrier transport, geometry and material dependent and structure calculations, role of metal and high-k material
interfaces, role of high-k on bandstructure and related phenomena to enable
development of 22 nm scale devices.
Candidates to be considered for this area are required to have a strong understanding of semiconductor physics and quantum effects in nanodevices.
The candidates are also expected to have a strong background in devices
physics, electronic structure methods, numerical programming, hands on
experience with ab-initio modeling tools, and computer programming in mixed language environment.
Should have Ph.D/MS in Physics, Electrical Engineering, Applied Physics, Computer Science, or Theoretical Materials Science.
For more details, visit the page where the offer is posted.... and polish your CV!
Oct 10, 2008
Oct 3, 2008
Job on Compact Modeling
Here you have an offer I've got from a groupmail in LinkedIn (please note that we're only posting it because it seems interesting to all those working on Compact Modeling, and looking for a change of position. We're in no way related to the people making the offer):
Looking for R&D Engineers for transistor level (MOSFET, FinFET, etc) research.(View discussion in LinkedIn.)
Looking for R&D Engineers for transistor level (MOSFET, FinFET, etc) research.(View discussion in LinkedIn.)
- PhD or MSc Microelectronics / Semiconductor Physics or equivalent
- Device Modeling/Simulation (TCAD)
- R&D experience with Universities or Fab/Foundry
Multiple vacancies in multiple Asian locations available. Email alex@maxima.com.sg for details.
[mos-ak] Edinburgh on-line publications
I post an e-mail from Wladek Grabinski (MOS-AK), in the MOS-AK googlegroups:
The MOS-AK Edinburgh Workshop's presentations are available on-line
please visit:
http://www.mos-ak.org/edinburgh/
I would like to take this opportunity and thank all speakers and presenters for their valuable contribution to the MOS-AK/ESSDERC/ESSCIRC workshop.
Let me also acknowledge the workshop sponsors (Accelicon, Tanner, X-FAB and SUSS) for their generous financial support as well as the conference organizers for their support, smooth organization and perfect logistic of our modeling event, which is an unique platform for continuous promotion of local, European compact modeling activities.
You are more than welcome to attend and contribute to coming events:
# 1st International MOS-AK Workshop in San Francisco
http://www.mos-ak.org/sanfrancisco/
# MOS-AK Spring'09 Meeting
http://www.mos-ak.org/frankfurt_o/
Oct 2, 2008
On the way to Plastic computation
I've found (out of sheer luck, I must say) a very nice paper in the IEEE Circuits and Systems Magazine. The topic: Plastic electronics, one of my fixations, even if I think that it will be used mainly for large-area applications. The paper I'm talking about (On the way to plastic computation) is a quite complete paper, from fabrication to circuit design using a commercial soft (Cadence).
The only point I find improvable (a lot) is that they are not doing a good job in the references, and they miss a lot of the field. However, as I've said, the paper is very interesting (not for the technical aspects, but this is a magazine...), since it's the first time I see a paper presenting the full design cycle...
The only point I find improvable (a lot) is that they are not doing a good job in the references, and they miss a lot of the field. However, as I've said, the paper is very interesting (not for the technical aspects, but this is a magazine...), since it's the first time I see a paper presenting the full design cycle...
Sep 30, 2008
2009 Symposium on VLSI Technology
The 2009 IEEE Symposium on VLSI Technology will be held from June 15 to June 17 at Rihga Royal Hotel in Kyoto, Japan.
The IEEE Symposium on VLSI Technology is one of the most prestigeous conferences on VLSI devices and processes. It is also a very competitive and tough conference. Papers should always be innovative enough regarding VLSI devices. Some of the topics explicitly mentioned in the Call for Papers are "processes and device modeling of VLSI devices" and "theories and fundamentals" related to VLSI devices. Therefore, researchers in device modeling (including compact modeling) can submit papers to the IEEE Symposium on VLSI Technology, but it should be remarked that these models or theories should be real breakthroughs.
The deadline is January 14.
There will be a Best Student Paper Award. The Symposium will cover the travel mexpenses and registration fee for the award recipient to attend the 2009 Symposium.
The IEEE Symposium on VLSI Technology will be held in conjunction with the IEEE Symposium on VLSI Circuits, which is one of the top conferences in the field of integrated circuits. This Symposium is also very demanding and competitive. Papers should be really breakthroughs to be accepted.
Besides, a satellite workshop, the 2009 Silicon Nanoelectronics Workshop, will be held at the same location as the VLSI Symposia on June 13-14 2009.
Well, despite the symposium is so demanding, it is worthy to work hard to make a suitable paper for this Symposium. And it is also a good opportunity to enjoy some days in Kyoto, one of the most beautiful cities in Japan!
The IEEE Symposium on VLSI Technology is one of the most prestigeous conferences on VLSI devices and processes. It is also a very competitive and tough conference. Papers should always be innovative enough regarding VLSI devices. Some of the topics explicitly mentioned in the Call for Papers are "processes and device modeling of VLSI devices" and "theories and fundamentals" related to VLSI devices. Therefore, researchers in device modeling (including compact modeling) can submit papers to the IEEE Symposium on VLSI Technology, but it should be remarked that these models or theories should be real breakthroughs.
The deadline is January 14.
There will be a Best Student Paper Award. The Symposium will cover the travel mexpenses and registration fee for the award recipient to attend the 2009 Symposium.
The IEEE Symposium on VLSI Technology will be held in conjunction with the IEEE Symposium on VLSI Circuits, which is one of the top conferences in the field of integrated circuits. This Symposium is also very demanding and competitive. Papers should be really breakthroughs to be accepted.
Besides, a satellite workshop, the 2009 Silicon Nanoelectronics Workshop, will be held at the same location as the VLSI Symposia on June 13-14 2009.
Well, despite the symposium is so demanding, it is worthy to work hard to make a suitable paper for this Symposium. And it is also a good opportunity to enjoy some days in Kyoto, one of the most beautiful cities in Japan!
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