Article in EDN: Modeling gaps in state-of-the-art mixed-signal SOC design

I've recently found an old (2006) paper on the EDN: Electronics Design, Strategy, News website. (I cannot reproduce it here because of the copyrights).

They discuss a bit about standardization efforts on Compact Modeling, and the different aspects that must be taken into account. I think it is a nice paper, even though it is slightly biased towards BSIM (only a bit: PSP, EKV and HiSIM are also mentioned... but not so extensively....).

Papers in Volume 52, Issue 5, Pages 597-838 (May 2008) of Solid-State Electronics

It seems that this month's harvest has been quite good. There are some quite interesting papers

Low-frequency noise properties of double channel AlGaN/GaN HEMTs
S.K. Jha, C. Surya, K.J. Chen, K.M. Lau and E. Jelencovic

A fully 2-dimensional, quantum mechanical calculation of short-channel and drain induced barrier lowering effects in HEMTs
G. Krokidis, J.P. Xanthakis and N.K. Uzunoglu

Subthreshold characteristics of polysilicon TFTs
Wanling Deng, Xueren Zheng, Rongsheng Chen and Yuan Liu

Physics-based 1/f noise model for MOSFETs with nitrided high-κ gate dielectrics
Tanvir Hasan Morshed, Siva Prasad Devireddy, Zeynep Çelik-Butler, Ajit Shanware, Keith Green, J.J. Chambers, M.R. Visokay and Luigi Colombo

Modeling non-quasi-static effects in channel thermal noise and induced-gate noise in MOS field-effect transistors
Abhay Deshpande and R.P. Jinda

Mobility model for compact device modeling of OTFTs made with different materials
M. Estrada, I. Mejía, A. Cerdeira, J. Pallares, L.F. Marsal and B. Iñiguez

Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs
Sung Jun Jang, Dae Hyun Ka, Chong Gun Yu, Won-Ju Cho and Jong Tae Park

Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs
A. Cerdeira, O. Moldovan, B. Iñiguez and M. Estrada

MOS-AK

I copy a mail from Wladek Grabinski:

The MOS-AK Eindhoven Workshop's presentations are available on-line
please visit: www.mos-ak.org/eindhoven

I would like to take this opportunity and thank all speakers and presenters for
their valuable contribution to the MOS-AK Meeting at MiPlaza. Selected MOS-AK
publications are recommended for further publications: www.mos-ak.org/eindhoven

Let me also acknowledge the workshop sponsors (MiPlaza, Agilent and Cascade) for
their generous financial support as well as local meeting organizers for their
support, smooth organization and perfect logistic of our modeling event. Such
events are unique platform for continuous promotion of local, European compact
modeling activities.

You are more than welcome to attend and contribute to coming modeling events:
* WCM'08 Workshop June 1-5, 2008, Boston, Massachusetts
* MIXDES'08 June 19-21, 2008 Poznan www.mixdes.org/Special_sessions.htm
* MOS-AK/ESSDERC/ESSCIRC Workshop September 19, 2008 www.mos-ak.org/edinburgh/

An interesting paper

Have a look, and share (if you wish) your comments...

Charge transport in boron-doped nano MOSFETs: Towards single-dopant electronics
Applied Surface Science, In Press, Accepted Manuscript, Available online 12 March 2008
Y. Ono, M.A.H. Khalafalla, K. Nishiguchi, K. Takashina, A. Fujiwara, S. Horiguchi, H. Inokawa and Y. Takahashi

IMEC reports methodology to analyze process variability compatible with DFM tools

It seems that, looking through the inherent self-publicity, the report (presented in DATE'08, by the way) is quite nice. I copy an excerpt here, but you can also access the full report in the original source.

Quoting Rudy Lauwereins, Vice President Nomadic Embedded Systems at IMEC:

"Up to now, most variability characterization work is done internally at IDMs on own technology and IP blocks. However, with the move to fabless and fablite companies, we want to bridge the gap between foundry and fabless companies on design-level impact of using most advanced semiconductor technologies. To this end, we invite IDMs, fabless system companies, fabless digital IP providers and foundries to collaborate within our Technology-Aware Design program to develop the necessary tools for designing reliable systems with variable and unreliable components. IMEC’s program is compatible with confidentiality constraints for high value proprietary IP blocks."

Interesting papers on Applied Physics Letters

Some interesting papers, that appear in this month's issue ( Appl. Phys. Lett. 92, 2008):

Drift mobility and the frequency response of diode connected organic transistors, Brian Cobb, Yeon Taek Jeong, and Ananth Dodabalapur
Abstract

Effects of substrates on photocurrents from photosensitive polymer coated carbon nanotube networks, Yumeng Shi, Hosea Tantang, Chun Wei Lee, Cheng-Hui Weng, Xiaochen Dong, Lain-Jong Li, and Peng Chen
Abstract

Determining the interfacial density of states in metal-insulator-semiconductor devices based on poly(3-hexylthiophene), N. Alves and D. M. Taylor
Abstract

Carrier trapping and scattering in amorphous organic hole transporter, K. K. Tsung and S. K. So
Abstract

Talk in EPFL (Switzerland)

I've got a mail from EPFL, announcing the next meeting of the SSCS chapter of West-Switzerland. It is going to take place at EPFL, and you can see the exact room in the map, looking for room C0016. Moreover, there will be a talk from Xing Zhou. I copy the post here:

Title: New Challenges in MOS Compact Modeling for Future Generation CMOS

Presenter: Xing Zhou

School of Electrical & Electronic Engineering

Nanyang Technological University

50 Nanyang Avenue,

Singapore 639798

Where: EPFL, Building CO, Room CO016 (http://plan.epfl.ch)

When: Tuesday, March 11, 2008, 17h00

Abstract: As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges to developing a compact model suitable for these new device structures and requires a paradigm shift in the core model structure. Conventional bulk-MOS models are based on four-terminal unipolar conduction in a doped channel with ideal symmetrical PN-junction source/drain contacts. In MG/NW MOSFETs, however, the device becomes three-terminal with undoped channel and possible bipolar conduction, and source/drain contacts become an integral part of intrinsic channel. Source/drain asymmetry, either intentional or unintentional, in a theoretically symmetric MOSFET also becomes important to capture in a compact model, which is nontrivial in a model that depends on terminal source/drain swapping at the circuit level. In this talk, after a brief review of the history of compact model development and various approaches, we discuss these new challenges and demonstrate solution methods based on the unified regional modeling (URM) approach.

Bio: Xing Zhou received the B.E. degree from Tsinghua University, Beijing, China, in 1983, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, NY, in 1987 and 1990, respectively. From 1990 to 1991, he was a research associate in the Department of Electrical Engineering, the University of Rochester, where he worked on hot-carrier injection phenomena in MOS devices, as well as development of CAD tools for mixed-signal circuit simulation. From 1992 to 1995, he was a research fellow in the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, where he worked on Monte Carlo and numerical modeling of semiconductor and optoelectronic devices as well as mixed-signal circuit modeling and simulation. He is currently a tenured associate professor in the same school at NTU, as well as program director and lab supervisor of the computational nanoelectronics group. His current research focuses on development of compact models for circuit simulation for conventional and emerging nanoscale MOS devices. In November and December of 1997 as well as in February and March 2001, he was a visiting fellow at the Center for Integrated Systems, Stanford University, California. In January 2003, he was a visiting professor at Hiroshima University, Japan. In May 2007, he was a visiting professor at Universiti Teknologi Malaysia. He is the founding chair of the Workshop on Compact Modeling (WCM) in association with the Nano Science and Technology Institute (NSTI) Nanotech Conference since 2002. He was the recipient of the 2006 NSTI Fellow award.

Dr. Zhou is an elected member of the IEEE Electron Devices Society (EDS) Administrative Committee, chair of the EDS Asia Pacific Subcommittee for Regions/Chapters, a member of the EDS Compact Modeling and VLSI Technology and Circuits technical committees as well as the Membership, Publications, and Educational Activities committees, and an EDS newsletter editor for Region 10 (Australia, New Zealand & South Asia). He has served as an EDS distinguished lecturer since 2000. Since 2007 Dr. Zhou is an editor of the IEEE Electron Device Letters.