Title: New Challenges in MOS Compact Modeling for Future Generation CMOS
School of Electrical & Electronic Engineering
Nanyang Technological University
50 Nanyang Avenue,
Singapore 639798
Where: EPFL, Building CO, Room CO016 (http://plan.epfl.ch)
When: Tuesday, March 11, 2008, 17h00
Abstract: As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges to developing a compact model suitable for these new device structures and requires a paradigm shift in the core model structure. Conventional bulk-MOS models are based on four-terminal unipolar conduction in a doped channel with ideal symmetrical PN-junction source/drain contacts. In MG/NW MOSFETs, however, the device becomes three-terminal with undoped channel and possible bipolar conduction, and source/drain contacts become an integral part of intrinsic channel. Source/drain asymmetry, either intentional or unintentional, in a theoretically symmetric MOSFET also becomes important to capture in a compact model, which is nontrivial in a model that depends on terminal source/drain swapping at the circuit level. In this talk, after a brief review of the history of compact model development and various approaches, we discuss these new challenges and demonstrate solution methods based on the unified regional modeling (URM) approach.
Bio: Xing Zhou received the B.E. degree from Tsinghua University, Beijing, China, in 1983, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, NY, in 1987 and 1990, respectively. From 1990 to 1991, he was a research associate in the Department of Electrical Engineering, the University of Rochester, where he worked on hot-carrier injection phenomena in MOS devices, as well as development of CAD tools for mixed-signal circuit simulation. From 1992 to 1995, he was a research fellow in the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, where he worked on Monte Carlo and numerical modeling of semiconductor and optoelectronic devices as well as mixed-signal circuit modeling and simulation. He is currently a tenured associate professor in the same school at NTU, as well as program director and lab supervisor of the computational nanoelectronics group. His current research focuses on development of compact models for circuit simulation for conventional and emerging nanoscale MOS devices. In November and December of 1997 as well as in February and March 2001, he was a visiting fellow at the Center for Integrated Systems, Stanford University, California. In January 2003, he was a visiting professor at Hiroshima University, Japan. In May 2007, he was a visiting professor at Universiti Teknologi Malaysia. He is the founding chair of the Workshop on Compact Modeling (WCM) in association with the Nano Science and Technology Institute (NSTI) Nanotech Conference since 2002. He was the recipient of the 2006 NSTI Fellow award.
Dr. Zhou is an elected member of the IEEE Electron Devices Society (EDS) Administrative Committee, chair of the EDS Asia Pacific Subcommittee for Regions/Chapters, a member of the EDS Compact Modeling and VLSI Technology and Circuits technical committees as well as the Membership, Publications, and Educational Activities committees, and an EDS newsletter editor for Region 10 (Australia, New Zealand & South Asia). He has served as an EDS distinguished lecturer since 2000. Since 2007 Dr. Zhou is an editor of the IEEE Electron Device Letters.
