A nice paper from Maria-Anna Chalkiadaki, Cédric Valla, Frédéric Poullet, and Matthias Bucher:
Why- and how- to integrate Verilog-A compact models in SPICE simulators
This article presents a fast and accurate way to integrate and validate Verilog-A compact models in SPICE-like simulators. Modifications in the models' Verilog-A source code may be required prior to their conversion into low-level C language by a code generator. The most common of these modifications is discussed. The generated C code is then directly compiled in the target simulator resulting in an equivalent SPICE model. The comparison between Verilog-A and SPICE models in the same simulation environment, for simple and complex circuits, validates the procedure. Performance tests for demanding designs are carried out for both models. Results highlight the higher simulation speed and lower memory consumption of SPICE models. Copyright © 2012 John Wiley & Sons, Ltd.
Jul 9, 2012
Birthday (61) of the JUNCTION transistor
From EDN:
Bell Labs and primarily William Shockley announced the invention of the junction transistor at a press conference in Murray Hill, NJ, the first week of July, 1951.
Sources vary as to when the formal announcement was actually made, July 4, 1951, or July 5, 1951.
At the time, Shockley was with Bell Labs’ solid state physics group, a unit to which he was a group head and a unit that saw much internal competition.
This new type of transistor overcame problems created by earlier point-contact transistors, developed by Bell Labs’ Joe Bardeen and Walter Brattain without Shockley but based in part on his previous work. It is said that when the patent process began for the point-contact transistor, Shockley made an effort to have his name only placed on the patent and made sure his fellow engineers knew of that effort.
Shockley has been described as having a “tremendous ego” by his co-workers. He was also known as having openly racist views.
Although Shockley is often known as “the inventor” of the transistor and despite his reported ego, he was often noted as correcting such misstatement and noting that he led the effort with others involved. Notes made during the development of the junction transistor can be viewed here.
Shockley left Bell Labs a few years after working on the junction transistor and eventually became a professor emeritus of electrical engineering at Stanford. He died on campus in 1989 at the age of 79.
For more moments in tech history, see this blog.
Bell Labs and primarily William Shockley announced the invention of the junction transistor at a press conference in Murray Hill, NJ, the first week of July, 1951. Sources vary as to when the formal announcement was actually made, July 4, 1951, or July 5, 1951.
At the time, Shockley was with Bell Labs’ solid state physics group, a unit to which he was a group head and a unit that saw much internal competition.
This new type of transistor overcame problems created by earlier point-contact transistors, developed by Bell Labs’ Joe Bardeen and Walter Brattain without Shockley but based in part on his previous work. It is said that when the patent process began for the point-contact transistor, Shockley made an effort to have his name only placed on the patent and made sure his fellow engineers knew of that effort.
Shockley has been described as having a “tremendous ego” by his co-workers. He was also known as having openly racist views.
Although Shockley is often known as “the inventor” of the transistor and despite his reported ego, he was often noted as correcting such misstatement and noting that he led the effort with others involved. Notes made during the development of the junction transistor can be viewed here.
Shockley left Bell Labs a few years after working on the junction transistor and eventually became a professor emeritus of electrical engineering at Stanford. He died on campus in 1989 at the age of 79.
For more moments in tech history, see this blog.
Jul 2, 2012
NANOTEC-Tutorial at ESSCIRC/ESSDERC in Bordeaux on 09/17/2012
The NANO-TEC project will held a half day tutorial at the ESSDERC/ESSCIRC Conference in Bordeaux on Monday, September 17, 2012. This Tutorial will be on the ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS in Europe and will present the current outcome of the EU project NANOTEC [read more...]
Jun 21, 2012
[mos-ak] C4P: Special Issue of IEEE TED on Advanced Modeling of Power Devices and Their Applications
Call for Papers
For the Special Issue of
IEEE Transactions on Electron Devices
On
Advanced Modeling of Power Devices and Their Applications
The special issue on "Advanced Modeling of Power Devices and Their Applications" is devoted to the research and development activities on power devices, the correlation of modeling approaches to the physics of power devices and in particular on emerging models of advanced power devices for power circuit applications.
The importance of accurate circuit design with power devices is increasing according to the necessity of realizing efficient energy consumption. High-voltage MOSFETs are also utilized in all kinds of consumer electronics, and electric vehicles are controlled by IGBT circuit, where an urgent task is to achieve better energy control at about 1 kV bias condition. Accurate and even predictable models based on a close correlation to the important physical effects occurring in such power devices are therefore highly desired for precise circuit design. Presently many investigations are also undertaken intensively for new materials such as SiC and GaN replacing Silicon for extremely high voltage applications e.g. beyond 10 kV. A good understanding of the device operation under such extremely high bias conditions requires a lot physical analysis, and as a result leads to more effective utilization of these power devices. Together with the strong self-heating effect, the dynamically changing resistivity makes convergence in circuit simulation unstable. Techniques and physical analysis to overcome such problems are also urgently requested.
Due to the wide range of covered bias conditions and the large variety of device structures applied, a lack of communication occurs in the high-voltage community even though the basic tasks are the same. Therefore, the objective of this special issue is to bring together a diversity of R&D activities and advancements in the physical analysis and modeling of MOS-based power devices and other types of emerging power devices including Bipolar, Thyristor and Diode. Models for active and passive components integrated in advanced silicon as well as new material technologies, statistical modeling and mixed-mode simulation are also of special interest.
The requirements for modeling high-voltage devices on the part of the circuit design community are now much more demanding due to urgent necessity to reduce energy consumption, where the high-voltage devices play an important role. Submissions should address advances in device characterization, physical models, as well as applications preferably but not limited to the following areas:
1. Compact modeling of power devices such as high-voltage MOSFETs, Bipolar, Thyristor and IGBT forcircuit applications from a few volts up to beyond 10kV.2. Modeling of passive elements such as Diode, Inductor, Resistor.3. Investigations on new material such as SiC and GaN and their applications.4. Circuit simulation for real applications of power devices together.5. Investigation for computation efficiency for circuit simulation
Please submit manuscript by using the following:
http://mc.manuscriptcentral.com/ted
http://mc.manuscriptcentral.com/ted
MAKE SURE TO MENTION THE SPECIAL ISSUE IN THE COVER LETTER
Paper Submission Deadline: July 15, 2012Scheduled Publication Date: February, 2013
Guest Editors:
Mitiko Miura-Mattausch, Hiroshima University, mmm@hiroshima-u.ac.jpNarain Arora, Silterra Malaysia, narain@silterra.comEhrenfried Seebacher, Austriamicrosystems AG, ehrenfried.seebacher@austriamicrosystems.comSamar K. Saha, SuVolta, Inc., samar@ieee.org
If you have any questions about submitting a manuscript, please contact:
IEEE EDS Publications Office
445 Hoes Lane Piscataway NJ 08854
Phone: +1 732 562 6855 Fax: +1 732 562 6831
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Jun 20, 2012
5th "Micro&Nano2012" Kokkini Hani, Heraklion, 7-10 October 2012
Fifth International Conference "Micro&Nano2012"
on Micro - Nanoelectronics, Nanotechnologies and MEMs
Aquis Arina Sand Hotel, Kokkini Hani, Heraklion
7-10 October 2012
on Micro - Nanoelectronics, Nanotechnologies and MEMs
Aquis Arina Sand Hotel, Kokkini Hani, Heraklion
7-10 October 2012
This is the first Micro&Nano conference, which will be organized at Heraklion, Grete, by members of the Micro&Nano society affiliated with the Foundation for Research and Technology (FORTH) and University of Crete. The conference will be co-chaired by Dr. Georgios Konstantinidis and Prof. Alexandros Georgakilas.
The Conference combines an extensive scientific programme including oral and poster sessions with exhibition and social events.
The Conference aims at gathering together in an interactive forum all scientists and engineers working in the challenging areas of micro/nano-electronic and optoelectronic/photonic devices, MEMs and circuits, as well as the enabling nanotechnologies of material growth, synthesis and processing. It aims to stimulate discussions on the last achievements and new developments in this rapidly evolving field.
One of the key objectives of the Conference is to promote collaboration and partnership between different academia, research and industry players. A one day workshop, presenting indicative cases and reviewing experiences and perspectives in these domains in Greece and elsewhere, will follow the conference [read more...]
The Scariest Graph
Posted from SemiWiki:
Everyone knows Moore's Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.
But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.
But look at this graph:
This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel's server business since those have such high margins that they can probably live with a price that doesn't come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don't live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).
If this graph remains the case, then Moore's Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.
Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn't make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won't happen. And just like there is no business selling "microprocessor design tools" since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for "14nm design tools" to justify the investment.
So that's why this is the scariest graph in EDA.
The Scariest Graph I've Seen Recently
by
Published on 06-18-2012 02:34 PM
10 Comments 
But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.
But look at this graph:
This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel's server business since those have such high margins that they can probably live with a price that doesn't come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don't live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).
If this graph remains the case, then Moore's Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.
Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn't make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won't happen. And just like there is no business selling "microprocessor design tools" since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for "14nm design tools" to justify the investment.
So that's why this is the scariest graph in EDA.
Jun 18, 2012
[mos-ak] [2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
[2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/
Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the the technical program sponsor, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.
http://mos-ak.org/bordeaux/
Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the the technical program sponsor, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.
Free on-line registration (open on June 18)
http://www.mos-ak.org/bordeaux/registration.php
The terms of participation, intending participants and authors should also note the following dates:
- Preannouncement - April 2012
- Call for Papers - May 2012
- Abstract submission deadline - July 2012
- On-line abstract submission (open on June 18):
- http://mos-ak.org/bordeaux/abstracts.php
- Final Workshop Program - Aug. 2012
- MOS-AK/GSA Workshop - Sept. 21, 2012 http://www.mos-ak.org/bordeaux/
- Morning Session
- Panel Discussion: "Status and Next Decade of European Compact Modeling"
- Poster Session
- Afternoon Session
Speakers (tentative list):
Prof. Maria Helena Fino, Universidade Nova Lisboa, PProf. Lidia Lukasiak, TU Warsaw, PLProf. Androula Nassiopoulou, IMEL Demokritos, GRProf. Elena Gnani, University of Bologna, IMunira Raja. Uni. Liverpool, UKMaria-Alexandra Paun, EPFL, CHSadayuki Yoshitomi, Toshiba, JPYogesh S. Chauhan, UC Berkeley, USAPatrick Martin, Minatec, FDaniel Tomaszewski, ITE Warsaw, PL
Further details and updates: <http://mos-ak.org/bordeaux/>
Email contact: <workshops@mos-ak.org>
- with regards - WG (for the MOS-AK/GSA Committee)
- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––
MOS-AK/GSA Bordeaux (F) Sept.21, 2012
MOS-AK/GSA San Francisco, CA Q4 2012
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