Post Doctoral Fellowship at UNIK (Norway), in Advanced CMOS Device Modeling

Position Description: One Post Doctoral fellowship for 18 months in the research group of Professor Tor A. Fjeldly in the area of advanced electronic device modeling, simulation and characterization.

The candidate will work at UNIK - University Graduate Center (www.unik.no)located near Oslo. UNIK is affiliated with University of Oslo (www.uio.no) and Norwegian University of Science and Technology (NTNU) (www.ntnu.no).
Terms of Employment: The salaries and terms at UNIK are in accordance with Norwegian governmental regulations. The annual salary for the post doctoral fellow is 435 000 NOK (about 81 000 USD as of mid-August 2008), including five weeks per year of paid vacation per year of actual service. Health benefits and full salary during illness are provided.

Project: The position is financed by the European Union project COMON - Compact Modelling Network, which is coordinated by Prof. Benjamin Iñiguez (Universitat Rovira i Virgili, Spain)

For a more detailed description of the project see:

http://brage.unik.no/personer/torfj/Projects/COMON/COMON_Annex.pdf

Research Topics:
• Compact modeling of nanoscale MOSFETs
• Model validation
• Parameter extraction techniques
• Model implementation

Startup and Deadline: Applicants are encouraged to apply at the earliest convenience. The deadline for the application is September 15, 2008. The startup date is flexible and can be chosen by the candidate in consultation with Professor Fjeldly. The COMON project is provisionally scheduled to start on October 1, 2008.

How to Apply: Applicants must submit official academic records for their bachelor, masters, and Ph.D. education, and a complete publication list. It is a requirement to hold a Ph.D. or an equivalent degree for being considered for this position. At least three academic references (name, position, e-mail, and telephone number) should be
included in the application.

Applicants are encouraged to submit their applications electronically to:
postmottak@unik.no and torfj@unik.no
Home-page of Prof. Fjeldly: http://brage.unik.no/personer/torfj
Office phone: +47-64844700 or +47-64844747
Otherwise, send by regular mail to:
UNIK - University Graduate Center
Attn: Tor A. Fjeldly
Instituttveien 25, P. O. Box 70
N-2027 Kjeller, Norway
Background: The candidates must have a solid background in electronics, semiconductor device physics, and mathematics. The ability to program in Matlab or other similar programming languages is also essential.
Candidate Evaluation Criteria: To evaluate the candidates, the following prioritized criteria will be used:
1) International publications (journal & conference) on relevant topics, i.e., scientific productivity and the time spent to produce the scientific work.
2) University education
• Grades: To be considered, the applicant should have mainly A or B for relevant courses and overall good grades
to demonstrate the capacity to learn new material
• The time used to complete the Bachelors, Masters, and Ph.D. university degrees should follow the normal study
time period
• Proficiency in English as documented by TOEFL, IELTS, or equivalent practical use of English.
• GRE score if available
• Completion of courses indicating relevant knowledge in
– Electronics
– Semiconductor device physics
– Mathematics
• Relevance of Ph.D. (and Masters) research topics
3) Industrial experience in electronics
4) Teaching experience
5) Females are given priority when competing with men of equal qualifications.
Description of UNIK - University Graduate Center: UNIK is a graduate educational institution for Master’s, graduate engineering and doctoral students, primarily affiliated with University of Oslo or Norwegian University of Science and Technology (NTNU), but also for continuing education students from commerce and
industry. Courses are offered in four academic fields:
• Electronics and Photonics
• Networking, Information Security, and Signal Processing for
Communications
• Cybernetics and Industrial Mathematics
• Energy and the Environment
UNIK offers courses and supervision on behalf of University of Oslo and NTNU. For more information see: www.unik.no.
Help to find a place to live: UNIK will help the chosen candidate to find a place to live near UNIK. UNIK will help the candidate and his/her family to sign up for courses in Norwegian language, if desired.

Papers on IEEE Trans on Electron Devices (Aug 2008)

Well, it seems that this has been a very productive issue:

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability
Millar, C. Reid, D. Roy, G. Roy, S. Asenov, A. (link)

Analytical Threshold Voltage Model for Double-Gate MOSFETs With Localized Charges
Kang, H. Han, J.-W. Choi, Y.-K. (link)

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs
Asenov, A. Cathignol, A. Cheng, B. McKenna, K. P. Brown, A. R. Shluger, A. L. Chanemougame, D. Rochereau, K. Ghibaudo, G. (link)

A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body
Liu, F. He, J. Zhang, L. Zhang, J. Hu, J. Ma, C. Chan, M. (link)

Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs
Hariharan, V. Vasi, J. Rao, V. R. (link)

A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs
Yu, B. Song, J. Yuan, Y. Lu, W.-Y. Taur, Y. (link)

A Quasi Two-Dimensional Conduction Model for Polycrystalline Silicon Thin-Film Transistor Based on Discrete Grains
Wong, M. Chow, T. Wong, C. C. Zhang, D. (link)

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET
Khan, H. R. Mamaluy, D. Vasileska, D. (link)

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation
Lenzi, M. Palestri, P. Gnani, E. Reggiani, S. Gnudi, A. Esseni, D. Selmi, L. Baccarani, G. (link)

A Physical Model of High Temperature 4H-SiC MOSFETs
Potbhare, S. Goldsman, N. Lelis, A. McGarrity, J. M. McLean, F. B. Habersat, D. (link)

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach
Rogdakis, K. Lee, S.-Y. Bescond, M. Lee, S.-K. Bano, E. Zekentes, K. (link)

Characterization, Modeling, and Application of 10-kV SiC MOSFET
Wang, J. Zhao, T. Li, J. Huang, A. Q. Callanan, R. Husna, F. Agarwal, A. (link)

Nice papers (July, 2008)

No, we're not dead, but overworked... Here you have some nice papers, from various sources, including one which is unexpected...

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET
Chung Ha Suh, Solid-State Electronics (abstract)

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond
Jeffrey B. Johnson, Terence B. Hook, and Yoo-Mi Lee, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, JULY 20 (abstract)

An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors
Yuan Liu, Student Member, IEEE, Ruo-he Yao, Bin Li, Member, IEEE, and Wan-Ling Deng, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 4, NO. 2, JUNE 2008 (abstract)

Papers on the IEEE TED, vol 55 (7)

Some nice papers:

An Analytical Gate Tunneling Current Model for MOSFETs Having Ultrathin Gate Oxides
Mondal, I.; Dutta, A. K.
Abstract

A Fully Three-Dimensional Atomistic Quantum Mechanical Study on Random Dopant-Induced Effects in 25-nm MOSFETs
Jiang, X.-W.; Deng, H.-X.; Luo, J.-W.; Li, S.-S.; Wang, L.-W.
Abstract

A Physical-Based PSPICE Compact Model for Poly(3-hexylthiophene) Organic Field-Effect Transistors
Meixner, R. M.; Gobel, H. H.; Qiu, H.; Ucurum, C.; Klix, W.; Stenzel, R.; Yildirim, F. A.; Bauhofer, W.; Krautschneider, W. H.
Abstract

IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation

The first IEEE International Workshop on Compact Thin-Film Transistor Modeling for Circuit Simulation will be held in the Moller Center, in Cambridge, UK, on September 11-12 2008.

This interesting workshop is organized by the IEEE EDS Compact Modeling Technical Committee, in collaboration with the London Center for Nanotechnology, University College of London, UK, the Electrical Engineering Division, Engineering Department, Cambridge University, UK, and the IEEE UK-RI (AP/ED/LEO/MTT) joint Chapter.

Compact modeling of TFTs has become nowadays a very hot topic, due to the extension of the applications of TFTs. This workshop will provide a forum for discussions and current developments on compact TFT modeling.

Topics include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The deadline for abstract submission is July 15.

I will give an invited presentation in this workshop. And there will be other interesting invited presentations.

This is the first workshop that is devoted to compact TFT modeling. I recommend the TFT modeling and TFT circuit design communities to attebnd this workshop.

Besides, in conjunction with the workshop on “Compact TFT Modeling for Circuit Simulation,” IEEE Electron Devices Society (EDS) Compact Modeling Technical Committee (CMTC) in collaboration with IEEE UK-RI AP/ED/LEO/MTT Chapter has organized EDS mini-colloquia (MQ) on September 12, 2008 at Moller Centre, Cambridge, UK.