DATE2025 FS06 Focus Session:
Date: Tuesday, 01 April 2025
Time: 11:00 CEST - 12:30 CEST
Location / Room: Rhône 1
Session chair:
Ulf Schlichtmann, TU Munich, DE
Session co-chair:
Holger Blume, Leibniz University Hannover, DE
Organisers:
Norbert Wehn, University of Kaiserslautern-Landau, DE
Lukas Krupp, University of Kaiserslautern-Landau, DE
| Time | Label |
Presentation Title
Authors |
|---|---|---|
| 11:00 CEST | FS06.1 |
PANEL: IMPROVING CHIP DESIGN ENABLEMENT FOR UNIVERSITIES IN EUROPE
Speaker : Norbert Wehn, RPTU University of Kaiserslautern-Landau, DE Authors : Matthew Venn 1 , Joachim Rodrigues 2 , David Atienza 3 , Ian O'Connor 4 , Andreas Brüning 5 and Patrick Haspel 6 1 Tiny Tapeout, ES; 2 Lund University, SE; 3 EPFL, CH; 4 Lyon Institute of Nanotechnology, FR; 5 FMD, DE; 6 Synopsys, DE Abstract The semiconductor industry is central to the European economy, particularly in the industrial and automotive sectors. Semiconductor fabrication and chip design are the two largest segments of the microelectronics value chain. While Europe is strengthening semiconductor fabrication and technology with considerable investments, e.g., in new fabs, chip design capabilities fall far short of the required capacities. The EU MicroElectronics Training, Industry and Skills (METIS) Report 2023 has shown that chip designers are the job profiles identified as the most difficult to find in the European microelectronics industry. European universities face many challenges hindering their ability to produce skilled graduates and contribute to the semiconductor ecosystem. While student interest in, e.g., AI is booming, we observe a decreasing interest in microelectronics. The main reasons for this are the high entry barriers for students, reinforced by the lack of chip design enablement in academia. Hence, there are ongoing initiatives in different European countries, on the EU level, and worldwide to strengthen chip design education and research. This focus session will bring together stakeholders of these initiatives from Europe and the USA to explore the critical challenges, opportunities, and potential strategies facing chip design enablement in European academic institutions. The session will be held in the panel format with active audience participation to guarantee inclusiveness and foster a broad view of the topic. |
Advances in machine learning (ML) over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications such as image classification. This seeks original submission on ML applications to the entire design flow of integrated circuits, from system-level design to manufacturing, from functional verification to testing, from design time to runtime, etc.
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