[paper] Virtual N2 PDK

Yiying Liu , Minghui Yin , Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, and Zhiqiang Li

Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025)

DOI: 0.1109/TVLSI.2025.3529504

1 EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
2 School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing (CN)
3 State Key Laboratory of Fabrication Technologies for Integrated Circuits, Beijing (CN)

Abstract: Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.

FIG: 3D view of the NSFET structure and layouts of SRAM bit cells:
(b) 111 SRAM cell, (c) 112 SRAM cell, and (d) 122 SRAM cell.

Acknowledgements: This work was supported in part by the Strategic Priority Research Program of Chinese Academy of Sciences (CAS) under Grant XDA0330401 and in part by CAS Youth Interdisciplinary Team under Grant JCTD-2022-07.

[paper] Lambert W function for nanoscale MOSFET modeling

A. Ortiz-Conde a, V.C.P. Silva b c, P.G.D. Agopian b c, J.A. Martino b, F.J. García-Sánchez a

Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling

Solid-State Electronics (2025) 109080,

DOI:10.1016/j.sse.2025.109080

a Solid-State Electronics Lab, Universidad Simón Bolívar, Caracas 1080 (VE)
b LSI/PSI/USP, Universidade de São Paulo, São Paulo (BR)
c Department of Electronic and Telecom. Eng., Universidade Estadual Paulista, São João Da Boa Vista (BR)

Abstract: The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved, modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.

FIG: The simulated transistor structural geometry and transfer characteristics of the three TCAD simulated nanosheet devices (symbols), together with the corresponding playbacks (lines) of the traditional model and modified model.

Data availability: Data will be made available on request.

[paper] FDSOI CMOS Cryogenic SPICE Models

P. Chava1, H. Alius2, J. Bühler1, A. R. Cabrera-Galicia1, C. Degenhardt1, T. Gneiting2, M. Harff1, T. Heide3, P. Javorka4, M. Lederer5, S. Lehmann4, M. Simon5, M. Su2, P. Vliex1, S. van Waasen1,6, C. Witt7, D. Zetzsche3

Evaluation of Cryogenic Models for FDSOI CMOS Transistors

16th IEEE Workshop on Low Temperature electronics, IEEE WOLTE16, Cagliari, Italy, Jun. 3-6, 2024

DOI: 10.34734/FZJ-2024-05369

1 Central Institute of Engineering (ZEA-2), Forschungszentrum Jülich GmbH, 52428, Jülich, (D)
2 AdMOS GmbH, 72636 Frickenhausen, (D)
3 Raycics GmbH, 01069 Dresden, (D)
4 GlobalFoundries, 01109, Dresden, (D)
5 Fraunhofer Institute for Photonic Microsystems IPMS, Center Nanoelectronic Technologies (CNT), 01109, Dresden, (D)
6 Faculty of Engineering, Communication Systems, University Duisburg-Essen, 47057 Duisburg, (D)
7 GlobalFoundries, Kapeldreef 75, 3001 Leuven, (B)

Abstract: Scalable quantum computers demand innovative solutions for tackling the wiring bottleneck to control an increasing number of qubits. Cryogenic electronics based on CMOS technologies are promising candidates which can operate down to deep-cryogenic temperatures and act as a communication and control interface to the quantum layer [1,2]. However, the performance of transistors used in these circuits is altered significantly when cooling from room temperature to cryogenic temperatures, which motivates accurate cryogenic modeling of transistors. We will report on cryogenic models tailored specifically for fully depleted silicon-on-insulator (FDSOI) transistors. We performed extensive DC characterization of transistors with subsequent modeling using the BSIM-IMG 102-9.6 model, which is the first version with a built-in cryogenic extension [3]. The preliminary models effectively represent the DC device behavior from 7 K up to room temperature. These models are used in industry standard EDA and simulation software, like Cadence Spectre. With the presented cryogenic models, we will show simulations at cryogenic temperatures. We will also compare the simulation results with the measured performance of a test chip in the temperature range from 7 K up to room temperature.

FIG: Measured and modeled transfer characteristics of a short-channel nMOST at T = 7 K

with measurement setup inside the cryogenic chamber  

Acknowledgements: This work was funded by the German Federal Ministry of Education and Research (BMBF), funding program “Quantum technologies - from basic research to market”, project QSolid (Grant No. 13N16149).

En hommage à Stefan Alexandru Cserveny

 

[FOSDEM'25] OpenPDK and FOSS CAD-EDA tools

FOSDEM is a free event for software developers to meet, share ideas and collaborate, it was organized for 25th subsequent time at ULB Solbosch Campus, Brussels, Belgium, between Feb. 1-2, 2025. One of FOSDEM DevRooms (conferences sessions) "Open Hardware and CAD/CAM" was organized to review most recent developments of the printed circuit board (PCBs) design tools, circuit (ICs) designs/simulations, 3D modeling and analysis and collaborative and team-based hardware design techniques among many other related activities. The contributors and supporters of the OpenPDK Initiative showcased these remarkable developments: 

Árpád Bűrmen: "VACASK and Verilog-A Distiller - building a device library for an analog circuit simulator"

Abstract: VACASK is a novel FOSS analog circuit simulator with a clear separation between device models (i.e. equations) and circuit analyses. It is based on the state of the art KLU sparse matrix library and utilizes the OpenVAF Verilog-A compiler for building its device models from Verilog-A sources. A comparison with other FOSS analog circuit simulators is presented and the roadmap for future development is discussed. A major obstacle in development of VACASK (and every other new simulator) is the implementation of legacy device models that boils down to writing tens of thousands of lines of C code. Legacy device models are used in several older PDKs as well as in models of a large number of discrete electronic components. A novel approach to implementing these device models is proposed: a converter from SPICE3 API-based C code into modern Verilog-A code. The performance of the converted models is compared to that of native SPICE3 models. At the present the converted models can be used in VACASK and Ngspice circuit simulators as well as in any other simulator that supports Verilog-A. The limitations of the approach are discussed. Some alternative use cases for the converter are proposed and a roadmap for its future development is presented.

Holger Vogt: "ngspice - XSPICE elemental devices made available in KiCad"

Abstract: XSPICE code models have been intrgrated into ngspice since starting the ngspice project. Currently 68 device models are available, ranging from simple elements like analog gain cells or digital inverters up to complex ones like a digital state machine, SRAMs, 3D table models or interfaces to digital Verilog building blocks compiled with Verilator. The simulation with digital blocks is fast, since event based. The interface between digital and analog blocks is automated. The use of the XSPICE code models has been hampered a bit due to their specific interfaces and the lack of graphical symbols of its elements for creating user readable circuit diagrams. So I have started a project to provide XSPICE code model support via the well-known KiCad/ngspice integration. It comprises of symbol library and its assiciated device models assembled in a subcircuit model library. In the talk I will inform about its concept and status and will present some application examples 

https://forum.kicad.info/t/simulation-with-xspice-code-models/56384 https://sourceforge.net/projects/ngspice/

Felix Salfelder and Al Davis: "Verilog-AMS in Gnucap"

Abstract: Gnucap is a Free versatile and modern, modular, analog and mixed-signal simulator. Verilog-AMS is a standardized behavioural language for analog and mixed-signal systems based on the IEEE 1364-2005 industry standard, commonly known as Verilog. Gnucap was invented to advance circuit simulator technology from around 1985, at the time SPICE was developed (1973-1993) at UC Berkeley. Gnucap was released under GPLv3+ in 2001 to avoid patent issues. Today, proprietary simulators supposedly implement the most efficient algorithms yet inspired by public research from the past century. Meanwhile, the Gnucap project is making progress harvesting the breakthroughs, for use in free/libre software. To address the interoperability across circuit design tools, and across modelling domains, Verilog-AMS was created. Verilog-AMS extends traditional Verilog by analog features known from SPICE, and permits models that interact with both the digital and analog domains. The standard expertly allows for vendor-independent representations of modern circuit designs.

1 In this talk, we will explain the new revision of our proposed IEEE 1364-2005 compliant schematic interchange format, and how seamless interaction will empower FOSS EDA tools. We will outline work in progress, possibly demonstrate an application, and hint at opportunities. We will explain how the interchange will extend towards PCB design and layout

2 We will summarise new mixed signal features available in modelgen-verilog. This includes monitored analog events, as well as discrete modelling in terms of user defined primitives. We will expand on the usefulness of discrete disciplines and "connect modules", and give an update on the implementation status.

3 On the algorithmic end, we have added a plugin interface for VLSI-ready matrix solvers to the zoo. We will highlight a new solver combining temporal sparsity with the time/space efficiency of "conventional sparse" LU decomposition. We will explain why Gnucap will outpace traditional (open source) solvers on virtually all instances, both small and big circuits.

Wladek Grabinski: "The IHP OpenPK Initiative: Status and RoadMap"

Abstract: In the field of semiconductor technology, compact modeling, and IC designs, the OpenPDK Initiative provides an international platform for discussing advanced technologies, fostering collaboration among industry and academic leaders in electronic design automation (EDA). We review selected R&D topics presented at a recent event by prominent academic researchers and industrial professionals who presented and discussed innovative approaches in CAD/EDA tools, techniques including compact/SPICE modeling, and IC design that address the demands of emerging semiconductor technology applications. However, the semiconductor industry also faces many challenges in maintaining the growth of its workforce with skilled technicians and engineers. To address the increasing need for well-trained workers worldwide, we must find innovative ways to attract skilled talent and strengthen the local semiconductor workforce ecosystem. The FOSS CAD/EDA tools with the recently available open access PDKs provide a new platform to connect IC design beginners, enthusiasts and experienced mentors to benefit from the collaboration opportunities enabled by the fast-growing open-source IC design movement. The collaborative development of open-source integrated circuit (IC) designs is becoming increasingly feasible due to the rapid expansion of OpenPDKs recently offered by SkyWater, GF and IHP with an open schedule of MPW Runs for FMD-QNC project in 2024-25. This paper demonstrates the FOSS CAD/EDA contribution to the SPICE/Verilog-A modeling/standardization, compete IC design flow (Xschem, Qucs-S, ngspice, Xyce, OpenVAF, OpenEMS, Magic, kLayout, OpenRoad), in addition selected, open-source examples of analog/RF and digital IC designs will be presented.