Jan 21, 2021

Jan 20, 2021

[paper] Publish or be ethical?

Mariola Paruzel-Czachura, Lidia Baran, Zbigniew Spendel 
Publish or be ethical? Publishing pressure and scientific misconduct in research 
First Published CC BY-NC 4.0 Dec. 18, 2020 
SAGE Journals: Research Ethics (2020) 
DOI: 10.1177/1747016120980562 

* Institute of Psychology, University of Silesia in Katowice, Poland

Abstract: The paper reports two studies exploring the relationship between scholars’ self-reported publication pressure and their self-reported scientific misconduct in research. In Study 1 the participants (N = 423) were scholars representing various disciplines from one big university in Poland. In Study 2 the participants (N = 31) were exclusively members of the management, such as dean, director, etc. from the same university. In Study 1 the most common reported form of scientific misconduct was honorary authorship. The majority of researchers (71%) reported that they had not violated ethical standards in the past; 3% admitted to scientific misconduct; 51% reported being were aware of colleagues’ scientific misconduct. A small positive correlation between perceived publication pressure and intention to engage in scientific misconduct in the future was found. In Study 2 more than half of the management (52%) reported being aware of researchers’ dishonest practices, the most frequent one of these being honorary authorship. As many as 71% of the participants report observing publication pressure in their subordinates. The primary conclusions are: (1) most scholars are convinced of their morality and predict that they will behave morally in the future; (2) scientific misconduct, particularly minor offenses such as honorary authorship, is frequently observed both by researchers (particularly in their colleagues) and by their managers; (3) researchers experiencing publication pressure report a willingness to engage in scientific misconduct in the future.
Fig: Ways in which respondents have infringed ethical principles

Founding: The current research was supported by Miniatura1 2017/01/X/HS6/01332 from the National Science Centre (NCN, Poland) to Mariola Paruzel-Czachura. Any opinions, findings, and conclusions or recommendations expressed in this material are those of them authors and do not necessarily reflect the views of the National Science Center. The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

Tracking a variety of #semi, which are affected by COVID-19. (Image source: Yole) https://t.co/oeNFCdXZTj https://t.co/8wV4D8PQR3


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January 20, 2021 at 10:58AM
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Jan 19, 2021

[paper] CNTFET Technology for RF Applications

Martin Hartmann1,2, Sascha Hermann1,2,3, Phil F. Marsh4, Christopher Rutherglen4
Dawei Wang5, Li Ding6, Lian-Mao Peng6, Martin Claus7
and Michael Schröter7 (Senior Member, IEEE)
CNTFET Technology for RF Applications:
Review and Future Perspective
(Invited Paper)
IEEE Journal of Microwaves, vol. 1, no. 1, pp. 275-287, 2021
DOI: 10.1109/JMW.2020.3033781

1Center for Microtechnology, Chemnitz University of Technology, Chemnitz, Germany
2Center for Advancing Electronics Dresden, Germany
3Fraunhofer Institute for Electronic Nanosystems, Chemnitz, Germany
4Carbonics Inc., Culver City, USA
5Carbon Technology Inc., Irvine, USA
6Key Laboratory for the Physics and Chemistry of Nanodevices 
and Center for Carbon-based Electronics,  Peking University, China
7Chair for Electron Devices and Integrated Circuits, Technical University Dresden, Germany


Abstract: RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.


Fig: (a) sketch of a T-shape top gate on 4" wafer and (b) corresponding SEM image,
(c) SEM image in false colors depicting a multifinger buried gate CNTFET on an 8" wafer.

Acknowledgement: This work was supported in part by the German Research Foundation (DFG) through the Cluster of Excellence “Center for Advancing Electronics Dresden” (EXC1056/1); in part by the Federal Ministry of Education and Research under the project reference numbers 16FMD01K, 16FMD02 and 16FMD03, under the individual DFG Grant SCR695/6%25; in part by the National Key Research & Development Program under Grant 2016YFA0201901; in part by the National Science Foundation of China under Grants 61888102 and 61671020; in part by the Beijing Municipal Science and Technology Commission under Grant Z181100004418011; in part by the King Abdulaziz City for Science and Technology (KACST); in part by the The Saudi Technology Development and Investment Company (TAQNIA); in part by the U.S. Army STTR Contract W911NF19P002; and in part by the SBIR programs from the U.S. National Science Foundation and the U.S. Air Force Research Laboratory.

Jan 18, 2021