Sep 21, 2020

[paper] Memristors in SPICE

Modeling networks of probabilistic memristors in SPICE
Vincent J. Dowling1, Valeriy A. Slipko2, Yuriy V. Pershin1
arXiv:2009.05189v1 [cs.ET] 11 Sep 2020
DOI: 10.13164/re.2020.0001

1Department of Physics and Astronomy, University of South Carolina, Columbia, SC 29208 USA
2Institute of Physics, Opole University, Opole 45-052, Poland

Abstract. Efficient simulation of probabilistic memristors and their networks requires novel modeling approaches. One major departure from the conventional memristor modeling is based on a master equation for the occupation probabilities of network states. In the present article, we show how to implement such master equations in SPICE. In the case studies, we simulate the dynamics of ac-driven probabilistic binary and multi-state memristors, and dc-driven networks of probabilistic binary and multi-state memristors. Our SPICE results are in perfect agreement with known analytical solutions. Examples of LTspice codes are included.
Fig: Ac-driven probabilistic binary memristor: (a) simulated circuit, (b) schematics of SPICE model, and (c) example of current-voltage curves found with SPICE simulations. The listing of SPICE model is given in Apendix.

Appendix: SPICE code examples
B1 0 p0 I=-gm(tau01,V01,V(Va))*V(p0)*u(V(Va))+gm(tau10,V10,-V(Va))*V(p1)*u(-V(Va))
B2 0 p1 I=gm(tau01,V01,V(Va))*V(p0)**u(V(Va))-gm(tau10,V10,-V(Va))*V(p1)**u(-V(Va))
C1 p0 0 1 IC=1
C2 p1 0 1 IC=.0
R2 Va 0 1k
R1 Va 0 10k
R3 VI 0 1k
B3 0 VI I=I(R1)*V(p0)+I(R2)*V(p1)
V1 Va 0 SINE(0 1 200 0 0 0 0)
.FUNC gm(x,y,z)1/(x*exp(-z/y))
.param tau01=3E5 V01=.05
.param tau10=3E5 V10=.05
.tran 0 .1 0.05 10E-7
.backanno
.end

Sep 18, 2020

[paper] Co-designing electronics with microfluidics


from Twitter https://twitter.com/wladek60

September 18, 2020 at 10:35AM
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Sep 17, 2020

[paper] Compact Model for MoS2 FETs

A physics-based compact model for MoS2 field-effect transistors
considering the band-tail effect and contact resistance
Yuan Liu1, Jiawei Zeng2, Zeqi Zhu1, Xiao Dong2 and WanLing Deng3
Japan Society of Applied Physics; Accepted Manuscript online 11 September 2020
1Guangdong University of Technology, Guangzhou, Guangdong, CHINA
2Jinan University, Guangzhou, Guangdong, CHINA
3Electronic Engineering, Jinan University, Guangzhou, GuangDong, 510630, CHINA

Abstract: In this paper, we present a compact surface-potential-based drain current model in molybdenum disulfide (MoS2) field-effect transistors (FETs). Considering variable range hopping (VRH) transport via band-tail states in MoS2 transistors, an explicit solution for surface potential has been derived and it provides a good description over different regions of operation by comparisons with numerical data. Based on charge-sheet model (CSM) which applies to drift-diffusion transport, the current expression including contact resistance and velocity saturation effect is developed. Furthermore, the presented model is validated and shows a good agreement with experiment data for MoS2 FETs. Keywords: molybdenum disulfide (MoS2), surface potential, current expression.


Fwd: September 2020 Newsletter: Planet-Scale Processing of Silicates

September 2020 Newsletter: Planet-Scale Processing of Silicates
In the eastern Sierra Nevada mountains, near Mammoth Lakes, California, is a geological phenomenon: a cliffside lined with thousands of 10-20 meter tall pillars of basalt. The organized rock columns are so incongruous with the surrounding high altitude pine forest that they seem supernatural. Shepherds who frequented the area in the 1800's named it the "Devil's Woodpile." Today, it's a popular park called the Devils Postpile National Monument.

To a MEMS engineer, this odd rock cliff bears a striking resemblance to
the columnar grains in thin film PZT or ZnO. What a mind bender to see
familiar shapes from SEM images towering overhead.

Like PZT or ZnO, a special set of environmental conditions created the Devils Postpile. It was not, however, the result of grain growth; instead, the Postpile formed from a pool of lava which then cracked into a network of polygons as it cooled. (More like misprocessed thick photoresist!)
A scale factor of 20 million: PZT with columnar grains (top)
compared to basalt columns (bottom).
On top of the Devils Postpile, one particular area has a smooth surface
which reveals the cross-sections of the polygonal columns, 50-100 cm in width. This most unusual stone patio was formed by the water, pressure, and motion of a passing Ice Age glacier, a massive-scale version of chemical mechanical polishing (CMP). Basalt rock is primarily composed of SiO2 (45-52% by weight) and other metal oxides, such as TiO2, Al2O3 and MgO; all familiar MEMS materials, just in a much larger format.
Ancient CMP: cross-section of basalt columns, polished flat
by a glacier. Note the fine lines that were created by
grit trapped in the moving glacier.
Four kilometers from the Postpile is the stunning 30 meter tall Rainbow 
Falls, etched through two layers of volcanic rock. The top masking layer
of rock is harder than the thick underlayer of softer rhyodacite. Water
pouring over the edge erodes the soft rock at a faster rate, leaving a
re-entrant cliff face and thereby creating a beautiful waterfall.

An idle thought while hiking on a hot summer day: Is geology just a
planet-scale version of MEMS processes?
Please note: AMFitzgerald's business operations are continuing normally despite COVID *and* California wildfires.
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A.M. Fitzgerald & Associates, LLC ("AMFitzgerald") provides complete solutions for MEMS product development. Our full service engineering capabilities include: custom MEMS design to specification, semi-custom RocketMEMS® pressure sensors, process integration, prototype and short-run fabrication, multiphysics finite element modeling, foundry selection and transfer with support through production, and technology strategy consulting. 

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[paper] Low-voltage, Non-volatile, Compound-semiconductor Memory Cell

Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cell
Ofogh Tizno, Andrew R. J. Marshall, Natalia Fernández-Delgado, Miriam Herrera, Sergio I. Molina
and Manus Hayne
Scientific Reports volume 9, Article number: 8950 (2019) 
DOI: 10.1038/s41598-019-45370-1

Abstract: Whilst the different forms of conventional (charge-based) memories are well suited to their individual roles in computers and other electronic devices, flaws in their properties mean that intensive research into alternative, or emerging, memories continues. In particular, the goal of simultaneously achieving the contradictory requirements of non-volatility and fast, low-voltage (low-energy) switching has proved challenging. Here, we report an oxide-free, floating-gate memory cell based on III-V semiconductor heterostructures with a junctionless channel and non-destructive read of the stored data. Non-volatile data retention of at least 10000s in combination with switching at ≤2.6 V is achieved by use of the extraordinary 2.1 eV conduction band offsets of InAs/AlSb and a triple-barrier resonant tunnelling structure. The combination of low-voltage operation and small capacitance implies intrinsic switching energy per unit area that is 100 and 1000 times smaller than dynamic random access memory and Flash respectively. The device may thus be considered as a new emerging memory with considerable potential.


FIG: Device structure a) Schematic of the processed device with control gate (CG), source (S) and drain (D) contacts (gold). The red spheres represent stored charge in the floating gate (FG). b) Cross-sectional scanning transmission electron microscopy image showing the high quality of the epitaxial material, the individual layers and their heterointerfaces.

Simulation Methods: The nextnano software package was utilised for mathematically modelling the energy band diagram of the memory device structure reported here, taking into account strain and piezoelectricity. Within this work, a self-consistent Schrödinger solver was used along with the Poisson and drift–diffusion equations to calculate the electron densities at equilibrium and under bias.