Neurotransistor MatLab Code

Eunhye Baek, Nikhil Ranjan Das, Carlo Vittorio Cannistraci, Taiuk Rim, Gilbert Santiago Cañón Bermúdez, Khrystyna Nych, Hyeonsu Cho, Kihyun Kim, Chang-Ki Baek, Denys Makarov, Ronald Tetzlaff, Leon Chua, Larysa Baraban and Gianaurelio Cuniberti

Intrinsic plasticity of silicon nanowire neurotransistors for dynamic memory and learning functions

Nat Electron (2020). 

DOI: 10.1038/s41928-020-0412-1

Abstract: Neuromorphic architectures merge learning and memory functions within a single unit cell and in a neuron-like fashion. Research in the field has been mainly focused on the plasticity of artificial synapses. However, the intrinsic plasticity of the neuronal membrane is also important in the implementation of neuromorphic information processing. Here we report a neurotransistor made from a silicon nanowire transistor coated by an ion-doped sol–gel silicate film that can emulate the intrinsic plasticity of the neuronal membrane. The neurotransistors are manufactured using a conventional complementary metal–oxide–semiconductor process on an 8-inch (200 mm) silicon-on-insulator wafer. Mobile ions allow the film to act as a pseudo-gate that generates memory and allows the neurotransistor to display plasticity. We show that multiple pulsed input signals of the neurotransistor are non-linearly processed by sigmoidal transformation into the output current, which resembles the functioning of a neuronal membrane. The output response is governed by the input signal history, which is stored as ionic states within the silicate film, and thereby provides the neurotransistor with learning capabilities.

FIG: Illustration of the structural similarity between the ion migration in the neurotransistor (left) and the membrane of a neuron cell in which the ionic current was modulated by a membrane potential (Vmemb) change in the case of the action potential (right)

Code availability: The MatLab code that supports the mathematical model in this article is available
at https://github.com/eunhye8747/MatLab-Code-Neurotransistor

Acknowledgements: This research was supported by the German Excellence Initiative via the Cluster of Excellence EXC1056 Center for Advancing Electronics Dresden (CfAED) and the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ICT Consilience Creative Program (IITP-R0346-16-1007) supervised by the IITP (Institute for Information & communications Technology Promotion). We acknowledge support from the Initiative and Networking Fund of the Helmholtz Association of German Research Centers through the International Helmholtz Research School for Nanoelectronic Networks (IHRS NANONET) (no. VH‐KO‐606) and German Research Foundation (DFG) via grants MA 5144/9-1, MA 5144/13-1 and MA 5144/14-1; BA4986/7−1, BA4986/8−1. Finally, we thank the INSA-DFG Bilateral Exchange Programme for financial support (IA/ DFG/2018/138, 12 April 2018). The authors thank S. Oswald (IFW Dresden) for the X-ray photoemission spectroscopy analysis of the ion-doped hybrid silicate films and M. Park (NamLab, Dresden) for the insightful discussion about the ionic polarization in the film. We thank R. Nigmetzianov (TU Dresden) for the film analysis.

[paper] Ge Twin-Transistor NVM with FinFET Structure

Siao-Cheng Yan, Chong-Jhe Sun, Meng-Ju Tsai (Student Member, Ieee), Lun-Chun Chen,

Mu-Shih Yeh (Member, IEEE), Chien-Chang Li, Yao-Jen Lee and Yung-Chun Wu (Member, IEEE)

Germanium Twin-Transistor Nonvolatile Memory with FinFET Structure

IEEE J-EDS vol. 8, pp. 589-593, 2020

DOI: 10.1109/JEDS.2020.2999616

Abstract: Germanium is a promising alternative material for use in advanced technology nodes because it exhibits symmetrical mobility of holes and electrons. Embedded nonvolatile memory (NVM) is essential in electronic devices with integrated circuit (IC) technology, including future Ge-based technology. In this paper, we demonstrate Ge twin-transistor NVM with a fin field-effect transistor (FinFET) structure. This Ge twin-transistor NVM exhibits high programming and erasing speeds and satisfactory reliability. Moreover, the masks and fabrication process of this Ge twin-transistor NVM are identical to those of Ge-channel FinFETs. Thus, Ge twin-transistor NVM is a promising candidate for embedded NVM applications in future high-performance Ge complementary metal–oxide–semiconductor technology (CMOS).

FIG:  (a) Schematic top view of the Ge Twin NVM with one fin,

and (b) process flow of the Ge Twin NVM

Acknowledgements: This work was supported in part by Ministry of Science and Technology, Taiwan, under contract MOST 108-2221-E-007-003, and in part by Taiwan Semiconductor Research Institute, Taiwan.

[paper] Statistical modelling of oTFT

Faris, T. M. and Winscom, C. J. 

Statistical modelling of organic thin film transistor behaviour

Organic Electronics (2020, 105846

DOI:10.1016/j.orgel.2020.105846 

Abstract: Three analyses of the expressions describing the electrical characteristics of organic thin film transistors (OTFT's) are presented. The first is the field-independent approach to mobility originally used for inorganic semiconductor materials, often referred to as the Square Law (SQL). The second is appropriate for both the Multiple Trapping and Release (MTR) and the Variable Range Hopping (VRH) descriptions of mobility, where dependence on a transverse field is consistent with the Universal Mobility Law (UML). The third is appropriate for the Extended Gaussian Disorder (EGD) description where an exponential dependence of mobility on the transverse field occurs. In each case master equations have been derived, including Schottky contact effects, where the polarity of the voltage drop across the source and drain contacts is correctly taken into account for the first time. The effect of the bulk semiconductor material beyond the accumulation layer is also accounted for, and defines the sub-threshold performance in a low-voltage regime. A new statistical modelling procedure has been developed to extract the key parameters of these expressions simultaneously from experimental data. For the analysis of TRANSFER data, no more than five parameters are used in the SQL, UML and EGD treatments. All three models are considered so that the effect the choice of model has on the extracted parameters can be revealed; analysis of data from different metallophthalocyanines is used to illustrate the different effects. When the contact resistances correctly take into account possible Schottky-like behaviour, all three descriptions provide equally excellent fits to the data from TRANSFER experiments.  In a following report, a family of copper phthalocyanine-related semi-conductors will be examined in detail using these new analysis procedures to explore the effect of non-peripheral substituent bulk, and aza-nitrogen replacement by CH, on mobility.

Fig: Comparison of Ohmic-only vs. Ohmic+Schottky contact resistance extractions for

the linear region of GdPc2 TRANSFER data for VD=-5V

Acknowledgements: A. K. Ray (Brunel University, Uxbridge) and A. K. Sharma (USAF Research Laboratory) are gratefully acknowledged for providing some resources and experimental data. DZP Technologies Ltd., UK and USAF Research Laboratory, Space Vehicles Directorate, USA are thanked for sponsoring the project, and providing support to TMF.

[paper] Hot Carrier Degradation in n-MOSFETs

S. Mahapatra and U. Sharma, 

Department of Electrical Engineering,

IIT Bombay, Mumbai 400076, India

A Review of Hot Carrier Degradation in n-Channel MOSFETs

Part I: Physical Mechanism

IEEE TED, vol. 67, no. 7, pp. 2660-2671, July 2020

DOI: 10.1109/TED.2020.2994302

Abstract: Transistor parametric drift due to conduction mode hot carrier degradation (HCD) in n-MOSFETs is reviewed, for long- and short-channel length (LCH) devices having different source/drain (S/D) junction structures. The HCD magnitude and time kinetics shape are discussed for stress under different gate (VG) and drain (VD) biases with varying VG/VD ratio, and without and with substrate bias (VB). Post-dc stress kinetics is discussed. The published data are qualitatively analyzed to identify the roles of different underlying physical mechanisms. In part II of this article, impacts of technology scaling and stress temperature (T) and comparison of dc and ac stress are discussed.

Fig: (a) Schematic of an LDD MOSFET. Carrier heating process, primary and secondary impact ionization, respectively, at VB=0V and VB < 0V, and gate injection are shown. Charges due to HCD in the channel (square), gate–drain overlap (triangle), and spacer (diamond) regions are shown. (b) Energy band diagram showing the energy thresholds for impact ionization, and electron and hole injection over their respective channel-oxide barriers. AHI process is illustrated at (VG–VD) > 0V.

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