Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs

— Wladek Grabinski (@wladek60) August 19, 2017

from Twitter https://twitter.com/wladek60

August 19, 2017 at 10:11AM
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A Threshold Voltage #Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects https://t.co/sEviQXJbB3

A Threshold Voltage #Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects https://t.co/sEviQXJbB3

— Wladek Grabinski (@wladek60) August 18, 2017

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August 18, 2017 at 01:42PM
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[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand

A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha

15th IEEE NEWCAS

Strasbourg, France, 2017, pp. 225-228

doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

[mos-ak] [Workshop Program] 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven Sept.11 2017

15th MOS-AK ESSDERC/ESSCIRC Compact Modeling Workshop

Leuven; Monday Sept.11, 2017 (8:30-17:00)

Workshop Program online http://www.mos-ak.org/leuven_2017/ 

Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and Jean-Michel Sallese, EPFL (CH), Daniel Tomaszewski, ITE (PL), MOS-AK Technical Program Coordinators as well as all the Extended MOS-AK TPC Members, we have pleasure to invite to the 15th consecutive MOS-AK workshop organized as an integral part of the ESSDERC/ESSCIRC Conferences in Leuven on Sept.11, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Final Program of 15th MOS-AK ESSDERC/ESSCIC Workshop is available online:

http://www.mos-ak.org/leuven_2017/

Venue: 

KU LEUVEN Campus of Social Sciences 

(Parkstraat 45, 3000 Leuven) 

room AV 91.12

Online MOS-AK/Leuven Workshop Registration:

http://www.esscirc-essderc2017.org/howtoregister

(any related inquiries can be sent to register@mos-ak.org)

The MOS-AK workshop will be followed by four session of the ESSDERC Track4 "Device and Circuit Compact Modeling". These four lecture sessions include one invited and 14 pear reviewed papers in the compact/SPICE modeling and Verilog-A standardization domain:

Tuesday September 12, 2017 (11:00-12:20)

Cross-Domain Compact Modeling  

Chair: Wladek Grabinski - MOS-AK; Cristell Maneux - U-Bordeaux;

Tuesday September 12, 2017 (14:00-15:20)

Parameter Extraction  

Chair: Thierry Poiroux - CEA

Tuesday September 12, 2017 (16:40-18:00)

Modeling of Emerging Devices  

Chair: Jean-Michel Sallese - EPFL; Daniel Tomaszewski - ITE;

Wednesday September 13, 2017 (14:20-15:40)

Traps and Noise  

Chair: Benjamin Iniguez - URV; Sadayuki Yoshitomi - Toshiba;

MOS-AK Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication

in a special issue of the International Journal of High Speed Electronics and Systems 

Extended MOS-AK Committee

WG170817

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Review of commercial SiC MOSFET models: Topologies and equations - IEEE Xplore #paper https://t.co/LS090HojeE

Review of commercial SiC MOSFET models: Topologies and equations - IEEE Xplore #paper https://t.co/LS090HojeE

— Wladek Grabinski (@wladek60) August 16, 2017

from Twitter https://twitter.com/wladek60

August 16, 2017 at 11:22AM
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