[Call for Papers] ESSCIRC–ESSDERC 2017

September 11-14, 2017

LEUVEN - Belgium
www.esscirc-essderc2017.org

ESSCIRC–ESSDERC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits: MAKE SURE TO BE PART OF IT!

CALL for PAPERS

GUESS WHO IS COMING!

LOCAL SCIENTIFIC SECRETARIAT
​Cor Claeys (imec, BE) | General Chair
Chantal Deboes (imec, BE) | ESSDERC Chair
Danielle Vermetten (KU Leuven, BE) | ESSCIRC Chair

ORGANIZERS   

TECHNICAL CO-SPONSORSHIP
ESSDERC FINANCIAL SPONSOR 
ESSCIRC FINANCIAL SPONSOR 
DIAMOND SPONSOR  

ORGANIZING SECRETARIAT: Sistema Congressi s.r.l. 

[online] Verilog-AMS Quick Reference and Tutorials

Verilog-AMS is a hardware description language that can model both analog and digital systems. The official description of the Verilog-AMS language is contained in the Verilog-AMS Language Reference Manual.

This site is designed to be your quick reference guide for Verilog-A and Verilog-AMS. The reference material is not complete at this point, but is still quite usable. Over time the reference material should fill out and be supplemented with useful application notes and annotated models that will help you learn to use Verilog-A/MS more effectively. The emphasis is very much on analog and mixed-signal modeling. If you are looking for information on synthesis or the obscure corners of the Verilog language, you must look elsewhere

• Verilog-AMS Quick Reference
• The Verilog-AMS Language
• Verilog-AMS Tutorials
• Glossary
• Index
• Search

Both Ken & Henry at Designer’s Guide Consulting aim to make www.VerilogAMS.com your everyday source for information on Verilog-A/MS. Please take a look around, and tell your friends and co-workers. If you have questions about Verilog-AMS, feel free to ask them on
the forum at designers-guide.org.

QUCS mentioned in IEEE-EDL paper

Jacopo Iannacci, Fondazione Bruno Kessler (FBK), Trento, Italy, has recently published an article in the IEEE Electron Device Letters (EDL) where he used and explicitly mentioned the QUCS, FOSS CAD/EDA simulator:

RF-MEMS Technology for Future Mobile and High-Frequency Applications:

Reconfigurable 8-Bit Power Attenuator Tested up to 110 GHz

J. Iannacci, M. Huhn, C. Tschoban and H. Pötter

in IEEE EDL, vol. 37, no. 12, pp. 1646-1649, Dec. 2016.

Abstract: In this letter, we present and test—to the best of our knowledge, for the first time—, an 8-bit (256-state) reconfigurable RF-MEMS attenuator, from 10 MHz up to 110 GHz, realized in the CMM-FBK technology. Resistive loads, in series and shunt configuration, are selectively inserted on the RF line by means of electrostatic MEMS ohmic switches. The network exhibits several attenuation levels in the range of −10/−45 dB that are rather flat up to 50 GHz, and a certain number of configurations with VSWR smaller than 4 from nearly dc up to 110 GHz, and better than 2 on a frequency span of ~80 GHz.

doi: 10.1109/LED.2016.2623328

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7726036&isnumber=7739309]

Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers

Top #opensource #conference picks for #2017 https://t.co/nJzg2bSbpq #papers

— Wladek Grabinski (@wladek60) December 14, 2016

from Twitter https://twitter.com/wladek60

December 14, 2016 at 10:37AM
via IFTTT

[paper] A surface potential large signal model for AlGaN/GaN HEMTs

A surface potential large signal model for AlGaN/GaN HEMTs

Q. Wu, Y. Xu, Z. Wen, Y. Wang and R. Xu

2016 11th EuMIC, London, UK, 2016, pp. 349-352

doi: 10.1109/EuMIC.2016.7777562

Abstract: This paper presents an accurate analytical surface-potential-based compact model for AlGaN/GaN HEMTs for SPICE-like circuit simulation. Considering the important energy level E₀, an easy-implemented analytical continuous expression for the fermi level position E_f was deduced to obtain the surface potential (SP) φ_s. Then analytical core models for intrinsic charge and drain current are derived based on φ_s. The model has been implemented in Agilent ADS by using symbolic defined device. Excellent agreement of DC I-V, fundamental output power, power added efficiency and gain is obtained for the first time compared with measurement results. Moreover, the effect of physical parameter such as the barrier thickness d on device characteristic is researched on the basic of this model. The results show that the proposed physical based model can be useful for technological parameters analysis and optimization of process.

[read more: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7777562&isnumber=7777458]