Mar 3, 2014

[mos-ak] [Final Program] Spring MOS-AK Workshop in London

Spring MOS-AK Workshop in London
Together with the workshop host, Prof. Bal Virdee, Londonmet, FIET MIEEE, and Prof. Mike Brinson, Londonmet, as well as Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the spring MOS-AK Workshop in London

Venue:
London Metropolitan University 
166-220 Holloway Road
London N7 8DB

with On-line Free Registration 
  • March 28, 2013
    • 9:00-9:30 Open On-site Registration 
    • 9:30-12:00 Morning Session
    • 13:00-16:00 Afternoon Session
    • 17:00-19:00 Welcome Reception and Networking
  • March 29, 2013
    • 9:00-12:00 Qucs and ngspice GPL circuit simulation session

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Feb 22, 2014

14 Free Resources To Learn About MOSFETs


Metal Oxide Field Effect Transistors (MOSFET) are commonly used for amplifying or switching electronic signals. They have a wide usage in the field and learning about these is crucial for any electronic engineer. So, with that in mind, here are 14 resources that will get you up and running!

[Tutorials, Videos, Free Reference Materials at efytimes.com]

Custom IC Design & Device Modeling - Tools and Technologies


Synopsys University Symposium

Friday, March 7; 9:00 a.m. to 5:30 p.m; The Lalit New Delhi Hotel

The Synopsys University Symposiums are for members of the academic community to get the latest information on design automation solutions, methodologies and standards. These FREE technical seminars are a resource to help accelerate innovation. Join us at this symposium to learn how you can achieve the highest value and productivity from your Synopsys tool investment.

Device Modeling
With growing device and design complexity, device-circuit co-design is becoming an increasingly important area of research. Today, devices and circuits are designed and optimized together for superior performance, yield and reliability. Synopsys TCAD tools are indispensable for device design and optimization.

[Agenda on-line]

Feb 20, 2014

postdoc position in Spain related to semiconductor device modeling

As Professor in the Universitat Rovira i Virgili (Tarragona, Catalonia, , Spain), I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, junctionless nanowires, III-V MOSFETs, GaN HEMTs, Tunnel FETs, and also organic and metal oxide TFTs.

The candidate should be a person who holds a PhD as awarded after September 1 2009, or who is committed to defend his Ph D thesis in the coming months (before the start of the contract).

Contracts are expected to start after September 2014.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile.

The work may continue the work we did in the framework of some EU-funded projects, such as COMON (about Multi-Gate MOSFETs, GaN HEMTs, and High Voltage MOSFETs), SQWIRE (junctionless Si nanowires) and FlexNET (organic TFTs) . Our contribution in these projects was the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects.

The postdoc position, which will be a contract, will have a duration of up to 2 years. The net salary will be around 1900 Euro/months.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: February 24 2014

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Address:
Benjamin IƱiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona, Catalonia
SPAIN.

Feb 7, 2014

Standards For FinFETs

   http://electronicdesign.com/eda/synopsys-rich-goldman-explains-effects-standards-2014s-semiconductor-trends 

Rich Goldman, VP of corporate marketing and strategic alliances at Synopsys, recently predicted the top five trends that are likely to drive the global semiconductor industry in 2014. Standards will help, or hurt, each of these trends.

The ever-changing semiconductor industry has experienced and will continue to experience megatrends like no other industry. Recently, Rich Goldman, vice president of corporate marketing and strategic alliances at Synopsys, made his predictions about the top five trends that are likely to drive the global semiconductor industry in 2014. Each of these trends can be helped, or hurt, by the domain of standards.

Standards For FinFETs

Karen: You predict that FinFETs will be one of the top five trends in 2014. FinFETs promise lower power consumption and higher performance. Designing and manufacturing FinFETs involve a slew of challenges. How can standards help overcome some of them?

Rich: EDA tools and models are advancing to handle the unique properties and behaviors of FinFETs. For each step in the design cycle, data is transferred from one tool to another. Enabling interoperability and modeling are obvious roles for standards to play and there are already several standards in use today. For example, the Liberty library modeling standard is used to develop FinFET libraries that feed logic synthesis and other advanced tools. Standards for describing low-power design intent are also important. Because low power consumption is a key feature of FinFETs, designers can benefit from using these during the power planning stage. The Unified Power Format (UPF) (IEEE Std. 1801) is effective in capturing the low-power design intent and directing the EDA tools to implement it. The biggest advancements in standards for FinFETs are in the Interconnect Technology Format (ITF) standardized by the IEEE-ISTO and in the new BSIM-CMG (CMOS Multi-Gate) SPICE model.

Karen: Are these standards sufficient for FinFETs today?

Rich: Standards for advanced semiconductor design, including FinFETs, should always evolve. While the standards may suffice for a given technology or geometry node, design and EDA engineers are constantly inventing more effective ways of overcoming challenges. As these engineers learn new techniques, the standards for interoperability and modeling need to be enhanced. It’s a cyclical situation. The standards enable new designs that can render the standards obsolete unless the standards are updated to include new methods and technology. Thus, standards working groups, comprised of tech-savvy engineers and experts in standards development, are part of the overall success of new technologies such as FinFETs.