Jun 20, 2012

The Scariest Graph

Posted from SemiWiki:



The Scariest Graph I've Seen Recently

Everyone knows Moore's Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives the semiconductor industry. It is much better to look at Moore's Law the other way around, namely that the cost of any given functionality implemented in semiconductors halves every couple of years. It is this which has meant that you can buy (or even your kid can buy) a 3D graphics console that contains graphics way beyond what would have cost you millions of dollars 20 years ago in a state of the art flight simulator.

But look at this graph:


This shows the cost for a given piece of functionality (namely a million gates) in the current process generation and looking out to 20nm and 14nm. It is flat (actually perhaps getting worse). This might not matter too much for Intel's server business since those have such high margins that they can probably live with a price that doesn't come down as much as it has done historically. And they can make real money by putting more and more onto a chip. But it is terrible for businesses like mobile computing that don't live on the bleeding edge of the maximum number of transistors on a chip. If you are not filling up your 28nm die and a 20nm die costs just the same (and is much harder to design) why bother? Just design a bigger 28nm die (there may be some power savings but even that is dubious since leakage is typically an increasing challenge).

If this graph remains the case, then Moore's Law carries on in the technical sense that you can put twice as many transistors on your chip if you can think of something clever to do with them and can find a way to keep enough of them powered on. But it means there is no longer an economic driver to move to a new process unless you have run out of space on the old one.

Since EDA mostly makes money on designs in new processes (because they need new tools which can be sold at a premium) this is bad for EDA. It actually doesn't make money on the first few designs coming through a new process because there is so much corresponding engineering to be done. But if the mainstream never moves, the cash-cow aspect of selling EDA tools to the mainstream won't happen. And just like there is no business selling "microprocessor design tools" since there are too few groups who would buy them and their needs are too different, there might never be a big enough market for "14nm design tools" to justify the investment.

So that's why this is the scariest graph in EDA.

Jun 18, 2012

[mos-ak] [2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012

[2nd announcement] 10th MOS-AK/GSA ESSDERC/ESSCIRC Workshop in Bordeaux, Sept. 21, 2012
http://mos-ak.org/bordeaux/

Together with the Organizing Committee, Extended MOS-AK/GSA TPC Committee, and the IEEE EDS French Branch, the the technical program sponsor, we have pleasure to invite to the 10th MOS-AK/GSA Compact Modeling Workshop at the ESSDERC/ESSCIRC Conference in Bordeaux, Sept. 21, 2012.  

Free on-line registration (open on June 18) 
http://www.mos-ak.org/bordeaux/registration.php

The terms of participation, intending participants and authors should also note the following dates: 
  • Preannouncement - April 2012
  • Call for Papers - May 2012
  • Abstract submission deadline - July 2012
  • Final Workshop Program - Aug. 2012
  • MOS-AK/GSA Workshop - Sept. 21, 2012 http://www.mos-ak.org/bordeaux/
    • Morning Session
    • Panel Discussion: "Status and Next Decade of European Compact Modeling"
    • Poster Session 
    • Afternoon Session
Speakers (tentative list): 
Prof. Maria Helena Fino, Universidade Nova Lisboa, P
Prof. Lidia Lukasiak, TU Warsaw, PL
Prof. Androula Nassiopoulou, IMEL Demokritos, GR
Prof. Elena Gnani, University of Bologna, I
Munira Raja. Uni. Liverpool, UK
Maria-Alexandra Paun, EPFL, CH
Sadayuki Yoshitomi, Toshiba, JP
Yogesh S. Chauhan, UC Berkeley, USA
Patrick Martin, Minatec, F
Daniel Tomaszewski, ITE Warsaw, PL

Further details and updates: <http://mos-ak.org/bordeaux/
Email contact: <workshops@mos-ak.org

- with regards - WG (for the MOS-AK/GSA Committee
––––––––––––––––––––––––––––––––––---------------- 
COMON Tranining Course Tarragona (SP) June 28-29, 2012
MOS-AK/GSA Bordeaux (F) Sept.21, 2012 
MOS-AK/GSA San Francisco, CA Q4 2012 
––––––––––––––––––––––––––––––––––---------------- 

Special IETE issue on Compact Modeling

Special IETE issue (May-June 2012 Volume 58; Issue 3 Page Nos. 179-242) on Compact Modeling: "Compact Modeling as a Bridge between Scaled Semiconductor Technologies and Advanced Designs of the Integrated Circuits" is available on-line with following articles:
  1. A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation p. 181
    Mike E Brinson, Stefan Jahn, H Nabijou
  2. Aging Model for a 40 V Nch MOS, Based on an Innovative Approach p. 191
    Filippo Alagi, Roberto Stella, Emanuele Viganó
  3. Complex 2D Electric Field Solution in Undoped Double-gate MOSFETs p. 197
    Mike Schwarz, Thomas Holtij, Alexander Kloes, Benjamín Iñíguez
  4. 2D Analytical Calculation of the Parasitic Source/Drain Resistances in DG-MOSFETs Using the Conformal Mapping Technique p. 205
    Thomas Holtij, Mike Schwarz, Alexander Kloes, Benjamín Iñíguez
  5. RF Compact Modeling of High-voltage MOSFETs p. 214
    Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, Mingchun Tang
  6. HSPICE Model of the Physical Resistor p. 222
    Petr Beták, Petr Zavrel
  7. Enhanced Non-quasi-static Lauritzen Diode Model p. 226
    Lenka Sochová, Petr Beták, Ján Plojhár
  8. Self-heating Parameter Extraction of Power Metal-oxide-silicon Field Effect Transistor Based on Transient Drain Current Measurement p. 230
    Risho Koh, Takahiro Iizuka
  9. Extraction of Scalable Electrical Model for HV (600/800 V) MOS Transistors p. 237
    Lorenzo Labate, Simona Angela Cozzi, Roberto Stella

Jun 10, 2012

450mm Impact Report Now Available For Free Download

This unique and authoritative report identifies the activities required to attract investments and to support 450mm and other advanced research, innovation, prototyping and semiconductor production. This report was based on a 14-month study Future Horizons undertook, together with the French market research firm Decision, between January 2011 and February 2012.

A copy of the report can be downloaded from the Commission's website at: http://cordis.europa.eu/fp7/ict/nanoelectronics/documents/450mm-final-report.pdf

If you have any questions on the report on some of the wider 450mm issues, please do so via our website at www.futurehorizons.com or call +44 1732 740440.

Jun 6, 2012

[mos-ak] 2nd Training Course on Compact Modeling: Registration Open

The MOS-AK Group as main dissemination partner of the European COMON Compact Modeling Network is announcing series of the modeling events:
Visit also the compact modeling calendar at www.mos-ak.org

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