I couldn't resist the temptation to share this...
Oct 28, 2010
TriQuint rolls new GaAs foundry process
RF chip maker TriQuint Semiconductor Inc. has released its latest 150-mm gallium arsenide (GaAs) commercial foundry process. The process, dubbed TQP15, is targeted at the Ka-band segment. It is designed for building millimeter wave (mmWave) MMICs for applications such as VSAT, satellite communications and point to point radios [read more...]
Oct 27, 2010
New papers (October 27, 2010)
- Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis (abstract)
- Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method (abstract)
- A Physics-Based Compact Model for Polysilicon Resistors (abstract)
- The Equivalent-Thickness Concept for Doped Symmetric DG MOSFETs (abstract)
- An Analytical I–V Model for Surrounding-Gate Transistors That Includes Quantum and Velocity Overshoot Effects (abstract)
- Failure of the Scalar Dielectric Function Approach for the Screening Modeling in Double-Gate SOI MOSFETs and in FinFETs (abstract)
- Device Physics and Characteristics of Graphene Nanoribbon Tunneling FETs (abstract)
- Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges (abstract)
And other papers that I've found interesting:
- Dual Threshold Voltage Organic Thin-Film Transistor Technology (abstract)
- Complementary Organic Circuits Using Evaporated $ hbox{F}_{16}hbox{CuPc}$ and Inkjet Printing of PQT (abstract)
- Low-Voltage High-Performance Pentacene Thin-Film Transistors With Ultrathin PVP/High- $kappa$ HfLaO Hybrid Gate Dielectric (abstract)
- High-Performance Pentacene Thin-Film Transistors Fabricated by Organic Vapor-Jet Printing (abstract)
- Magnetic-Field Area Sensor Using Poly-Si Micro Hall Devices (abstract)
- On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits (abstract)
- On Undetectable Faults and Fault Diagnosis (abstract)
Oct 25, 2010
Job offers in LinkedIn: RF Modeling Device Engineer
Remember, this is only for information. We're not connected to them!
HIRING - Peregrine Semiconductor - RF Modeling Device Engineer
Click Here to Apply: https://home.eease.adp.com/recruit/?id=531727
Job Description:
This position is responsible for:
Member of team responsible for device modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process and packaging technology. The candidate will work closely with modeling engineers and CAD to support our design groups and external foundry customers.
Roles & Responsibilities will include:
• Responsible for modeling of passive components.
• Responsible for parasitic analysis of RF active components and BEOL.
• Model extraction for components on-wafer, modules, and packages.
• Manufacturing data analysis to develop statistical and corner models.
• Test chip DOE development, layout, and measurement.
• Provide guidance to design teams on best practice.
Qualifications:
Minimum Requirements:
• Ph.D. in Physics or Electrical Engineering (MS okay with demonstrated experience)
• Understanding of RF device performance metrics
• Experience using SPICE like circuit simulators to develop sub-circuit models.
• Experience using EM simulators (HFSS, Momentum, etc.) to study device performance.
• Demonstrated ability to extract models from measured data.
• Demonstrated problem solving skills.
The following traits are highly valued:
• Strong programming background and ability to develop automation scripts.
• Experience with Matlab, ICCAP, or other tool for model extraction.
• Layout optimization for RF applications.
• Experience configuring and automating test equipment.
• Large signal RF device characterization.
Job Description:
This position is responsible for:
Member of team responsible for device modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process and packaging technology. The candidate will work closely with modeling engineers and CAD to support our design groups and external foundry customers.
Roles & Responsibilities will include:
• Responsible for modeling of passive components.
• Responsible for parasitic analysis of RF active components and BEOL.
• Model extraction for components on-wafer, modules, and packages.
• Manufacturing data analysis to develop statistical and corner models.
• Test chip DOE development, layout, and measurement.
• Provide guidance to design teams on best practice.
Qualifications:
Minimum Requirements:
• Ph.D. in Physics or Electrical Engineering (MS okay with demonstrated experience)
• Understanding of RF device performance metrics
• Experience using SPICE like circuit simulators to develop sub-circuit models.
• Experience using EM simulators (HFSS, Momentum, etc.) to study device performance.
• Demonstrated ability to extract models from measured data.
• Demonstrated problem solving skills.
The following traits are highly valued:
• Strong programming background and ability to develop automation scripts.
• Experience with Matlab, ICCAP, or other tool for model extraction.
• Layout optimization for RF applications.
• Experience configuring and automating test equipment.
• Large signal RF device characterization.
Oct 15, 2010
[mos-ak] MOS-AK/GSA Seville Workshop Press Release
Press release:
"MOS-AK/GSA Modeling Working Group Holds Workshop in Seville"
can be found on the GSA site at
http://www.gsaglobal.org/news/article.asp?article=2010/1014
"MOS-AK/GSA Modeling Working Group Holds Workshop in Seville"
can be found on the GSA site at
http://www.gsaglobal.org/news/article.asp?article=2010/1014
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