HP and Hynix - Bringing the memristor to market in next-generation memory

Today, HP announced a joint development agreement with Hynix Semiconductor Inc., to develop a new kind of computer memory – one that will employ memristor technology pioneered by researchers at HP Labs.

LDMOS - Technology and Applications

Speaker: Shekar Mallikarjunaswamy, Alpha Omega Semiconductor
Date: Sept 14th, 2010
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara , CA 95051 .

Abstract: A key device that is used in most high voltage (20 to 120V) power integrated circuits for power management applications is the Lateral Diffused MOS (LDMOS) transistor. Recent interest in ‘green” products have further increased the demand for integrated HV LDMOS devices in CMOS and BCD technologies to build higher efficiency dc-dc converters for consumer and LED markets. This presentation will journey through the structural innovations from “planar” to “trench” and to state-of-the-art “RESURF” LDMOS devices in both junction and dielectric isolation technologies for the past two decades. The physics of operation, figure of merits used for device comparison, layout techniques including integration of LDMOS into modern CMOS/BCD technologies will be discussed. Device and process simulations to optimize device parameters including SPICE macro circuits to model “quasi-saturation” and “Cgd” capacitance will be described. Methods to improve hot carrier reliability and ESD robustness of LDMOS devices will be highlighted. Finally, LDMOS circuit topologies and their applications in consumer, computer and telecommunication products will be presented to let the audience comprehend and appreciate the significance of LDMOS devices to modern power management products.

Web link: http://www.ewh.ieee.org/r6/scv/eds/

Modeling Memristor with SPICE

In 1971, Professor Chua proposed [1] that by necessity of symmetry reasons, besides the resistor, the capacitor, and the inductor; a fourth circuit element has to exist. In 2008, members of an HP Lab published [2] that they successfully realized a nano-scale electronic component. Spice macromodel [3-6] could be a powerful tool for electrical engineers to design and experiment new circuits with memristors.

REFERENCES
[1] L. Chua, “Memristor: The missing circuit element,” IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507–519, Sep. 1971.
[2] D. B. Strukov, G. S. Snider, D. R. Stewart, and S. R. Williams, “The missing memristor found,” Nature, vol. 453, no. 7191, pp. 80–83, May 2008.
[3] H.H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," DATE, 2010.
[4] Á. Rak and G. Cserey, "Macromodeling of the Memristor in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, 2010, pp. 632-636.
[5] D. Batas and H. Fiedler, "A Memristor Spice Implementation and a New Approach for Magnetic Flux Controlled Memristor Modeling," IEEE Transactions on Nanotechnology, 2010, pp. 1-1.
[6] "Modeling the HP memristor with SPICE," http://www.neurdon.com/2010/07/23/modeling-the-hp-memristor-with-spice/, 2010.

How To Make a P-N-P-N Semiconductor Device

50 years ago this year, in its 'Patent Pointers' section, the Electronics Weekly edition of September 14th 1980 carried the following snippet.

'An ingenious way of making a P-N-P-N or an N-P-N-P semiconductor device which avoids the difficulty of the heat treatment of the second junction adversely affecting the first formed junction is described in Patent No. 844970, filed by British Thomson-Houston Co.'

The note continues:
'What is done is to form a first P-N junction by alloying semiconductor germanium of N type with semiconductor silicon of P type, the second junction being subsequently made by fusing indium to the germanium.'

The note ends:
'The second junction is made at a lower temperature than the first so that the first junction is unharmed.'

Posted by David Manners on August 17, 2010; TrackBack URL for this entry:
http://www.electronicsweekly.com/cgi-bin/mt/mt-tb.cgi/162252

DATE 2011 - Final Call for Papers

DATE 2011 - Conference and Exhibition
March 14-18, 2011; Grenoble, France

Submission Deadlines:

• Sept. 5, 2010: Papers, Special Sessions, Tutorials, Workshops
• Oct. 10, 2010: Exhibition Theatre
• Nov. 12, 2010: PhD Forum
• Jan. 14, 2011: University Booth

More Information:
Download/View the CfP as PDF
Complete DATE 2011 information is available