ESSDERC 2008 will be held in Edinburgh, Scotland from 15-19 September 2008, together with ESSCIRC 2008 (European Solid-State Circuits Conference) . The venue will be the Edinburgh International Conference Centre (EICC).
ESSDERC (European Solid-State Device Research Conference) is the top European conference in semiconductor devices. Due to its prestige, many researchers from outside Europe use to submit contributions to ESSDERC too.
The main themes for original contributions to be submitted to ESSDERC 2008 are:
-Advanced Devices
-Process Integration
-Telecommunication & Power Devices
-Modeling and Simulation
-Charactrization and Reliability
-Memory, SoC & SiP
-Emerging Technologies, Sensors & Actuators
-Sensors and Imagers
-Integration of IC designs with other technologies and materials
-Yield and Reliability related technology developments
-Design for Manufacturabiliti
This year Compact Modeling is explicitly mentioned as one of the topics in the "Modeling and Simulation" theme.
The deadline for abstract submission is April 5 2008.
Besides, several related workshops will take place on September 19 2008 at the same location.
One of them will be the Autumn MOS-AK Meeting on Compact Modeling. Another workshop will be the so-called SINANO workshop, this time organized by the recently created SINANO Institute.
Ths social programme may be interesting this year. The Conference Dinner will be held at Murrayfield Stadium, the home of Scottish Rugby! And they say that the menu will be typically Scottish "preceded by a drinks reception". For sure, we expect a lot of high quality whisky during the Conference Dinner!
Feb 13, 2008
Feb 12, 2008
DCIS'08
In 2008 DCIS (Conference on Design of Circuits and Integrated Systems) will take place in Grenoble, in France, on November 12-14 2008. It will be organized by the TIMA Laboratory.
DCIS was originally the top Spanish Conference on Circuit Design. However, more than 10 years ago it became an international conference. Although often held in Spain it has also been organized in other countries not far from Spain, such as Portugal or France.
The Call for Papers mentions all topics related to Integrated Circuit and Systems Design. As usual, modeling is included among the topics.
The submission deadline is April 4 2008.
Grenoble and its vicinity is a very nice place for sightseeing, offering many opportunities for outdoor: mountain trails to hike, historic buildings to see, old streets to walk along, and even skiing in the highest mountains in November.
DCIS was originally the top Spanish Conference on Circuit Design. However, more than 10 years ago it became an international conference. Although often held in Spain it has also been organized in other countries not far from Spain, such as Portugal or France.
The Call for Papers mentions all topics related to Integrated Circuit and Systems Design. As usual, modeling is included among the topics.
The submission deadline is April 4 2008.
Grenoble and its vicinity is a very nice place for sightseeing, offering many opportunities for outdoor: mountain trails to hike, historic buildings to see, old streets to walk along, and even skiing in the highest mountains in November.
New modeling papers in Solid-State Electronics
The February 2008 issue of Solid-State Electronics includes several interesting papers on compact modeling of different devices.
"A new analytical compact model for two-dimensional finger photodiodes", by T. Naeve et al
"An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET", by H. Kaur et al
"Extraction of series resistance using physical mobility and current models for MOSFETs", by H. Katto
"An explicit surface-potential-based model for undoped double-gate MOSFETs", by J. F. Gong et al
"An efficient channel segmentation approach for a large-signal NQS MOSFET model" by M. Bucher and A. Bazigos. This is a very interesting paper presenting an adequate technique to extend a compact Quasi-Static model to the RF operation.
I also recommend the following paper for reading (it is modeling of balistic devices although not compact modeling)
"Modeling the effects of the channel electron velocity on the channel surface potential of ballistic MOSFETs", by L. F. Mao
And there is a very interesting paper studying the capacitance characteristics of pentacene TFTs:
"Quasi-static capacitance–voltage characterizations of carrier accumulation and depletion phenomena in pentacene thin film transistors", by Y. M. Chen et al
The January issue of Solid State Electronics included a quite interesting paper by Huaxin Lu, Bo Yu and Yuan Taur, presenting a unified charge modelling formulation valid for both Double-Gate and Surrounding Gate MOSFETs:
"A unified charge model for symmetric double-gate and surrounding-gate MOSFETs", by Huaxin Lu, Bo Yu and Yuan Taur
A few compact modeling papers were also published in the December issue of Solid-State Electronics:
First of all, a compact model for power MOSFETs:
"An EKV-based high voltage MOSFET model with improved mobility and drift model", by Yogesh Singh Chauhan, Renaud Gillon, Benoit Bakeroot, Francois Krummenacher, Michel Declercq and Adrian Mihai Ionescu
And finally, a paper presenting an industrial view of compact modeling, indicating some special requirements that are important when developing physics-based compact models:
"An industrial view on compact modeling", by Reinout Woltjer, Luuk Tiemeijer and Dick Klaassen
"A new analytical compact model for two-dimensional finger photodiodes", by T. Naeve et al
"An analytical threshold voltage model for graded channel asymmetric gate stack (GCASYMGAS) surrounding gate MOSFET", by H. Kaur et al
"Extraction of series resistance using physical mobility and current models for MOSFETs", by H. Katto
"An explicit surface-potential-based model for undoped double-gate MOSFETs", by J. F. Gong et al
"An efficient channel segmentation approach for a large-signal NQS MOSFET model" by M. Bucher and A. Bazigos. This is a very interesting paper presenting an adequate technique to extend a compact Quasi-Static model to the RF operation.
I also recommend the following paper for reading (it is modeling of balistic devices although not compact modeling)
"Modeling the effects of the channel electron velocity on the channel surface potential of ballistic MOSFETs", by L. F. Mao
And there is a very interesting paper studying the capacitance characteristics of pentacene TFTs:
"Quasi-static capacitance–voltage characterizations of carrier accumulation and depletion phenomena in pentacene thin film transistors", by Y. M. Chen et al
The January issue of Solid State Electronics included a quite interesting paper by Huaxin Lu, Bo Yu and Yuan Taur, presenting a unified charge modelling formulation valid for both Double-Gate and Surrounding Gate MOSFETs:
"A unified charge model for symmetric double-gate and surrounding-gate MOSFETs", by Huaxin Lu, Bo Yu and Yuan Taur
A few compact modeling papers were also published in the December issue of Solid-State Electronics:
First of all, a compact model for power MOSFETs:
"An EKV-based high voltage MOSFET model with improved mobility and drift model", by Yogesh Singh Chauhan, Renaud Gillon, Benoit Bakeroot, Francois Krummenacher, Michel Declercq and Adrian Mihai Ionescu
And finally, a paper presenting an industrial view of compact modeling, indicating some special requirements that are important when developing physics-based compact models:
"An industrial view on compact modeling", by Reinout Woltjer, Luuk Tiemeijer and Dick Klaassen
Feb 11, 2008
NANOSIL kick-off meeting
NANOSIL is the name of a new European Commission-funded Network of Excellence devoted to the research in nanodevices, mostly based on Silicon. NANOSIL is the continuation of a previous Network of Excellence called SINANO (2004-2007).
NANOSIL started on January 1 2008 and will have a duration of three years. The kick-off meeting took place in Grenoble (France) on January 29 2008.
NANOSIL aims to integrate the excellent European research laboratories and capabilities at the European level in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits. It will explore and assess all scientific and technological aspects of nanodevices (mostly based on Silicon) and operational regimes relevant to the 22nm technology node and beyond. Therefore, NANOSIL will provide a forward-look for the industry, enabling informed decisions to be taken on technology development to speed up technological innovation.
Compact modeling is one of the activities in the Flagship Projects. My group will be mostly involved in that task. We plan to develop compact models of the novel devices addressed by NANOSIL.
Besides, NANOSIL will organize workshops and a modeling summer school.
NANOSIL started on January 1 2008 and will have a duration of three years. The kick-off meeting took place in Grenoble (France) on January 29 2008.
NANOSIL aims to integrate the excellent European research laboratories and capabilities at the European level in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits. It will explore and assess all scientific and technological aspects of nanodevices (mostly based on Silicon) and operational regimes relevant to the 22nm technology node and beyond. Therefore, NANOSIL will provide a forward-look for the industry, enabling informed decisions to be taken on technology development to speed up technological innovation.
There are seven Flagship Projects in the areas of nanoscale CMOS (workpackage WP1) and post-CMOS (workpackage WP2), known as the “More Moore” and “Beyond-CMOS” domains. This work will be carried out through a network of joint processing, characterisation and modelling platforms. Alongside these technological Flagship Projects each workpackage also has a Visionary Project that will act as a forum to explore novel ideas bewteen academia and European industry.
The Flagship Projects will be "New Channel Materials" (including Strained SOI and GeOI devices), "Very Low Schottky Barrier MOSFETs", "Identification and appraisal of gate stack materials for the end of CMOS era", "Nanowires" (Silicon nanowires), "Carbon Electronics" (with emphasis on graphene devices), "Small slope nanoelectronic switch for low power integrated circuits”, and "Templated Self-Organization".
The Coordinator of NANOSIL will be Prof. Francis Balestra (INPG-MINATEC, Grenoble). A total 0f 28 European groups, including mine (URV, Spain), participate in NANOSIL.Compact modeling is one of the activities in the Flagship Projects. My group will be mostly involved in that task. We plan to develop compact models of the novel devices addressed by NANOSIL.
Besides, NANOSIL will organize workshops and a modeling summer school.
EUROSOI+
The European Commission approved in 2007 the funding of the continuation of EUROSOI, the European Thematic Network on SOI Technology, Devices and Circuits.
The new EUROSOI network will be called EUROSOI+ and will have aduration of three years, starting from January 1 2008.
The EUROSOI network organizes every year the EUROSOI workshop. This year it took place in Cork, Ireland, from January 23 to 25. The Chairman was Prof. Jean Pierre Colinge, from Tyndall National Institute (Cork).
The EUROSOI workshop is already consolidated as the main European event devoted to SOI technology, devices and circuits.
The kick-off meeting of the new EUROSOI+ network took place during the workshop. The coordinator of EUROSOI+ is Prof. Francisco Gamiz, from the University of Granada (SPAIN). He was also the coordinator of the previous EUROSOI network.
The members of EUROSOI+ are: University of Granada (Spain), INPG (France), UCL (Belgium), SOITEC (France), VTT (Finland), CISSOID (Belgium), IMEC (Belgium), Philips (The Netherlands), EPFL (Switzerland), ISP-Kiev (Ukraine), IUE (Austria), WUT (Poland), XFAB (Germany), Chalmers (Sweden), Uppsala University (Sweden), Queens University of Belfast (UK), University of Twente (The Netherlands), CNRS (France), IMMS (Germany), CSIC (Spain), University of Liverpool (UK), POLITO (Italy), Universitat Rovira i Virgili (Spain), Umiversitat Autonoma de Barcelona (Spain), Universidad de Salamanca (Spain), UNIUD (Italy), Ditocom (France), CEA-LETI (France), ISEP (France) and Tyndall National Institute (Ireland).
The main goals of EUROSOI+ will be to support and increase collaborations between European groups regarding research in SOI technology, and to elaborate a roadmap and a state of the art documents about SOI technology. The website of EUROSOI is regularly update to include all news related to SOI.
Compact modeling of SOI devices is one of the topics addressed by EUROSOI+. Actually, I will be mostly in charge of the writing of the parts related to compact modeling in the roadmap and a state of the art documents.
The EUROSOI workshop in Cork was interesting and of real high level. Every participant got a gift that was very useful in Ireland: an umbrella.
The new EUROSOI network will be called EUROSOI+ and will have aduration of three years, starting from January 1 2008.
The EUROSOI network organizes every year the EUROSOI workshop. This year it took place in Cork, Ireland, from January 23 to 25. The Chairman was Prof. Jean Pierre Colinge, from Tyndall National Institute (Cork).
The EUROSOI workshop is already consolidated as the main European event devoted to SOI technology, devices and circuits.
The kick-off meeting of the new EUROSOI+ network took place during the workshop. The coordinator of EUROSOI+ is Prof. Francisco Gamiz, from the University of Granada (SPAIN). He was also the coordinator of the previous EUROSOI network.
The members of EUROSOI+ are: University of Granada (Spain), INPG (France), UCL (Belgium), SOITEC (France), VTT (Finland), CISSOID (Belgium), IMEC (Belgium), Philips (The Netherlands), EPFL (Switzerland), ISP-Kiev (Ukraine), IUE (Austria), WUT (Poland), XFAB (Germany), Chalmers (Sweden), Uppsala University (Sweden), Queens University of Belfast (UK), University of Twente (The Netherlands), CNRS (France), IMMS (Germany), CSIC (Spain), University of Liverpool (UK), POLITO (Italy), Universitat Rovira i Virgili (Spain), Umiversitat Autonoma de Barcelona (Spain), Universidad de Salamanca (Spain), UNIUD (Italy), Ditocom (France), CEA-LETI (France), ISEP (France) and Tyndall National Institute (Ireland).
The main goals of EUROSOI+ will be to support and increase collaborations between European groups regarding research in SOI technology, and to elaborate a roadmap and a state of the art documents about SOI technology. The website of EUROSOI is regularly update to include all news related to SOI.
Compact modeling of SOI devices is one of the topics addressed by EUROSOI+. Actually, I will be mostly in charge of the writing of the parts related to compact modeling in the roadmap and a state of the art documents.
The EUROSOI workshop in Cork was interesting and of real high level. Every participant got a gift that was very useful in Ireland: an umbrella.
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