MSM 2008

The 11th International Conference on Modeling and Simulation of Microsystems (MSM 2008) will be held in the Hynes Convention Center in Boston (Massachussets, USA) on June 1-5 2008, as part of the Nanotech 2008 Conference.

MSM is the main technical forum to present the latest research and development in design, modeling and simulation methods, tools and applications in the MEMS, microelectronic, semiconductor, sensor, materials and biotechnology fields. Process, device and circuit simulation is one of the topics explicitly mentioned. Semiconductors and Microelectronics is indicated as one of the application areas.

The Electronics and Microsystems suite of symposia at Nanotech 2008 has become a premier annual event in the Micro and Nano technologies arena. This Electronics and Microsystems suite of symposia is composed with the MEMS & NEMS, Sensors & Systems, Micro & Nano Fluidics symposia, andthe MSM conference The deadline for abstract submission is December 6 2007.

Selected proceedings papers in the Electronics and Microsystems Track (MEMS & NEMS, Sensors & Systems, Micro & Nano Fluidics symposia, and MSM conference) will be reviewed and invited into a Special Issue of the on-line magazine ‘Sensors & Transducers’ (S&T e-Digest).

WCM'08

The 2008 Workshop on Compact Modeling (WCM 2008) will be held in the Hynes Convention Center in Boston (Massachussets, USA) on June 1-5 2008, as part of the Nanotech 2008 Conference.

The Workshop on Compact Modeling (WCM) is one of the largest event devoted to the Compact Modeling field. WCM has become a very important open forum for discussion among experts in this field as well as feedback from technology developers, circuit designers, and EDA tool vendors.

The suggested topics include all important aspects of compact model development and application: intrinsic models, extrinsic/interconnec models, atom/quantum models, statistical models, and model extraction and interface.

A limited number of papers will be selected for oral presentations and the remaining accepted papers will be planned for poster presentations with oral briefing. The deadline for abstract submission is December 6 2007.

The Chairman of WCM is Professor Xing Zhou (from Nanyang Technological University, Singapore). He was the person who created WCM and has made this workshop very successful.

I think that it is a must for Compact Modeling researchers to attend WCM. Many of the last advances in this field are presented there.

IEEE TED and TNT Special Issue on Nanowire Electronics

IEEE Transactions on Electron Devices and IEEE Transactions on Nanotechnology have published a Call for Papers for a Joint Special Issue on Nanowire Electronics.

Suggested topics include Devices, Technology, Applications, Modeling and Quantum Simulations. Compact modeling for circuit design is explicitly mentioned as one of the topics.

The deadline for paper submission is April 30 2008, and the publication date will be November 2008.

New papers (APL)

Some new interesting papers on this month issue of Applied Physics Letters (APL):

Threshold voltage stability of organic field-effect transistors for various chemical species in the insulator surface
Kouji Suemori, Sei Uemura, Manabu Yoshida, Satoshi Hoshino, Noriyuki Takada, Takehito Kodzasa, and Toshihide Kamata
Appl. Phys. Lett. 91, 192112 (2007) (3 pages)
Abstract

High performance n-channel thin-film transistors with an amorphous phase C₆₀ film on plastic substrate
Jong H. Na, M. Kitamura, and Y. Arakawa
Appl. Phys. Lett. 91, 193501 (2007) (3 pages)
Abstract

The influence of visible light on transparent zinc tin oxide thin film transistors
P. Görrn, M. Lehnhardt, T. Riedl, and W. Kowalsky
Appl. Phys. Lett. 91, 193504 (2007) (3 pages)
Abstract

Flexible programmable logic gate using organic ferroelectric multilayer
Satoshi Horie, Kei Noda, Hirofumi Yamada, Kazumi Matsushige, Kenji Ishida, and Shuichiro Kuwajima
Appl. Phys. Lett. 91, 193506 (2007) (3 pages)
Abstract

Numerical modeling study of the unipolar accumulation transistor
Stephen J. Fonash, Md Mash-hud Iqbal, Florin Udrea, and Piero Migliorato
Appl. Phys. Lett. 91, 193508 (2007) (3 pages)
Abstract

Interface effects on the external quantum efficiency of organic bulk heterojunction photodetectors
Y. Kim, M. Ballarotto, D. Park, M. Du, W. Cao, C. H. Lee, W. N. Herman, and D. B. Romero
Appl. Phys. Lett. 91, 193510 (2007) (3 pages)
Abstract

New online demo and tutorial from Mentor

Two new product demos/tutorials have been added to Mentor's online event library. Both events are available on-demand and you can attend one or both at your convenience. »   Online Tutorial: Approaching Yield in the Nanometer Age The Framework for an extensible DFM Methodology. Overview: As we dive deeper into the nanometer space, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield. Not only are more DRC rules required, but the rules are becoming much more complex in light of more manufacturing issues. Yet advanced DRC is still not enough. We must redefine the sign-off process itself to include a spectrum of new methods that assess design quality. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance. In the nanometer age, sign-off must include not only fundamental, rule-based physical verification and parasitic extraction, but also a set of automated technologies that help improve yield by enhancing the design itself. What you will learn: This tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like. DFM Tools demonstrated: Calibre YieldAnalyzer Calibre YieldEnhancer Calibre YieldServer Register/Play Tutorial   »   Product Demo: Calibre LVS Integrated Design Debug Environment Overview: This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow. What you will learn: How to easily track down IC design errors using Calibre LVS How to identify the locations of these errors in your design environment How Calibre interacts with the Cadence Virtuoso design creation environment How Calibre LVS can improve your productivity by reducing your LVS debugging time Tools demonstrated: Calibre LVS to verify your IC design Calibre RVE to visualize the results and identify them in the Cadence Virtuoso environment Calibre Interactive as a launch platform to re-run your verification once the design has been fixed Register/Play Demo

Mentor Graphics Corporation Website: http://www.mentor.com/products/ic_nanometer_design Email: DSM_info@mentor.com