Thursday, 8 November 2007

New online demo and tutorial from Mentor

ou're invited – Seminar: Reducing Verification Cycle Times with Calibre
Two new product demos/tutorials have been added to Mentor's online event library. Both events are available on-demand and you can attend one or both at your convenience.

»   Online Tutorial: Approaching Yield in the Nanometer Age
The Framework for an extensible DFM Methodology.

Overview:
As we dive deeper into the nanometer space, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve
yield.

Not only are more DRC rules required, but the rules are becoming much more complex in light of more manufacturing issues. Yet advanced DRC is still not enough. We must redefine the sign-off process itself to include a spectrum of new methods that assess design quality. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance.

In the nanometer age, sign-off must include not only fundamental, rule-based physical verification and parasitic extraction, but also a set of automated technologies that help improve yield by enhancing the design itself.

What you will learn:
This tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like.

DFM Tools demonstrated:
  • Calibre YieldAnalyzer
  • Calibre YieldEnhancer
  • Calibre YieldServer
Register/Play Tutorial
 
»   Product Demo: Calibre LVS Integrated Design Debug Environment

Overview:
This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow.

What you will learn:
  • How to easily track down IC design errors using Calibre LVS
  • How to identify the locations of these errors in your design environment
  • How Calibre interacts with the Cadence Virtuoso design creation environment
  • How Calibre LVS can improve your productivity by reducing your LVS debugging time
Tools demonstrated:
  • Calibre LVS to verify your IC design
  • Calibre RVE to visualize the results and identify them in the Cadence Virtuoso environment
  • Calibre Interactive as a launch platform to re-run your verification once the design has been fixed
Register/Play Demo
 
 

Mentor Graphics Corporation
Website: http://www.mentor.com/products/ic_nanometer_design
Email: DSM_info@mentor.com


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