Ultimate Medical #Hackathon: How Fast Can We Design and Deploy an #opensource #Ventilator? https://t.co/nCVKtlq28P https://t.co/vQWAkeEaZn

Ultimate Medical #Hackathon: How Fast Can We Design and Deploy an #opensource #Ventilator? https://t.co/nCVKtlq28P pic.twitter.com/vQWAkeEaZn

— Wladek Grabinski (@wladek60) March 12, 2020

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March 12, 2020 at 02:43PM
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How to write effective documentation for your #opensource project https://t.co/6ub8SQhZiv https://t.co/2bSdgsa884

How to write effective documentation for your #opensource project https://t.co/6ub8SQhZiv pic.twitter.com/2bSdgsa884

— Wladek Grabinski (@wladek60) March 12, 2020

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ESSCIRC ESSDERC 2020 | TPC Meeting goes VIRTUAL

GRENOBLE (FRANCE) - September 14-18, 2020

Dear TPC members,​

The safety and health of all ESSCIRC-ESSDERC TPC and Steering Committee members, and generally of IEEE SSCS and EDS members, volunteers, and attendees of SSCS and EDS events are our first priority. Given the currently sanitary situation related to corona-virus, and after consulting with our Steering Committee and SSCS and EDS direction, the ESSCIRC-ESSDERC 2020 Conference Organizing Committee has decided to organize a virtual paper selection meeting. We want to ensure a high scientific quality of the paper selection process, and we want to make sure each TPC member can provide high quality feedback in the same manner.

Regarding the different meeting:

• The virtual participation of ALL TPC members is mandatory
• We are currently working on the organization modalities, and we will inform you soon about the practical organization: phone bridges and screen sharing software will be put in place for each track in order to properly be able to discuss and select the best papers
• We will try to accommodate a time schedule fitting to most of WW time zones represented in our TPC
• The final dates of this virtual meeting will be very close to the initially scheduled one, i.e. May 18th 2020 for the TPC meeting, and May 19th for the SC meetings

The paper submission deadline stays the same, April 17th, and we strongly encourage you and your research teams to submit papers. As well, please do advertise among your personal networks the paper submission to our conference.

On a more positive note, ESSCIRC-ESSDERC 2020 paper selection meeting will be the first full virtual SSCS/EDS of such type of meeting. With this new experience, we will learn new ways to better serve our community and also reduce our carbon footprint.

Thank you very much for your understanding, and we count on the support of each and every TPC and SC member to make of ESSCIRC-ESSDERC 2020 a successful conference even in times of crisis!

Kind regards,

Andreia Cathelin, ESSCIRC TPC chair
Sylvain Clerc, ESSCIRC TPC co-chairFrancois
Andrieu, ESSDERC TPC chair
Maud Vinet, ESSDERC TPC co-chair
Thomas Ernst, General Chair
Dominique Thomas, General co-chair











x

Senior and Junior Researcher positions at URV, in Tarragona, Spain

The Nanoelectronic and Photonic Systems (NEPHOS) Group at the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV) in Tarragona, Spain, is looking for candidades for long-term Senior and Junior Researcher Contracts funded by URV and the Spanish Ministry of Science.

Candidates with less than 7 years of postdoctoral research outside Spain can apply for the Junior position, with a  minimu duration of 4 years.

Candidates with more than 7 years of postdoctoral research outside Spain can apply for the Junior position, which after 4 years can become permanent.

The selected candidates will propose  research and teaching project together with the hosting group at URV.

Candidates must have performed important contributions in the field of semiconductor devices.

The NEPJHOS Group at URV is currently working on the physics, characterization and modeling (in particular compact modeling) of emerging devices, and also in the fabrication and characterization of nanostructured organic photovoltaic devices. Regarding emerging devices, the present interests of the group at URV are the characterization and modeling of nanowire MOSFETs, GaN HEMTs, Graphene and 2D semiconductor FETs and organic and oxide TFTs. Other interests are the fabrication of polymeric TFTs and the modeling of organic solar cells.

Candidates must send their CVs, by March 18 to:

benjamin.iniguez@urv.cat

Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.

Tarragona is one of the most important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

#paper A 3D map of atoms in 2D materials [Nature Materials, doi:10.1038/s41563-020-0646-3] Scanning atomic electron tomography measurements reveal the 3D local structure around single dopant atoms in 2D transition metal dichalcogenides https://t.co/oeNFCdXZTj https://t.co/2zG0FdpduE

#paper A 3D map of atoms in 2D materials
[Nature Materials, doi:10.1038/s41563-020-0646-3]
Scanning atomic electron tomography measurements reveal the 3D local structure around single dopant atoms in 2D transition metal dichalcogenides https://t.co/oeNFCdXZTj pic.twitter.com/2zG0FdpduE

— Wladek Grabinski (@wladek60) March 10, 2020

from Twitter https://twitter.com/wladek60

March 10, 2020 at 04:15PM
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#paper: Guest Editorial for the special issue on devices and circuits for millimeter‐wave and THz applications by Yuehang Xu First published: 09 March 2020 https://t.co/886FiJL5zU https://t.co/xSbxKCGFub https://t.co/cbQzWbTh4Z

#paper: Guest Editorial for the special issue on devices and circuits for millimeter‐wave and THz applications by Yuehang Xu
First published: 09 March 2020https://t.co/886FiJL5zUhttps://t.co/xSbxKCGFub pic.twitter.com/cbQzWbTh4Z

— Wladek Grabinski (@wladek60) March 10, 2020

from Twitter https://twitter.com/wladek60

March 10, 2020 at 02:57PM
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François Anceau, Founder of CMP, has died. He was 80. "Today is a sad day for the entire CMP family," CMP’s Director Kholdoun Torki said. "François was a visionary, he influenced generations of microelectronic developments in France" https://t.co/K9ASeQmTsX #paper https://t.co/mT5RVrnxme

François Anceau, Founder of CMP, has died. He was 80. "Today is a sad day for the entire CMP family," CMP’s Director Kholdoun Torki said. "François was a visionary, he influenced generations of microelectronic developments in France"https://t.co/K9ASeQmTsX#paper pic.twitter.com/mT5RVrnxme

— Wladek Grabinski (@wladek60) March 10, 2020

from Twitter https://twitter.com/wladek60

March 10, 2020 at 11:23AM
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article reached 1500 reads

A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski and Y. Papananos, "An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs," in IEEE TED, vol. 58, no. 11, pp. 3751-3758, Nov. 2011.

Abstract: The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS, allowing to coherently determine VTH for the entire range of V DS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

CICC 2020 March 22 – March 25, 2020 Virtually from anywhere! https://t.co/6LMk0g4HDq #paper https://t.co/FTH07ngklp

CICC 2020
March 22 – March 25, 2020
Virtually from anywhere!
https://t.co/6LMk0g4HDq#paper pic.twitter.com/FTH07ngklp

— Wladek Grabinski (@wladek60) March 9, 2020

from Twitter https://twitter.com/wladek60

March 09, 2020 at 04:03PM
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The New Dates of SEMICON/FPD China 2020 https://t.co/m1znJk8eKK #paper https://t.co/nUAveoEvpl

The New Dates of SEMICON/FPD China 2020https://t.co/m1znJk8eKK#paper pic.twitter.com/nUAveoEvpl

— Wladek Grabinski (@wladek60) March 6, 2020

from Twitter https://twitter.com/wladek60

March 06, 2020 at 01:15PM
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#paper: Y. Liu, S. Yang and K. Sheng, "Design and Optimization of Vertical GaN PiN Diodes With Fluorine-Implanted Termination," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 241-250, 2020 doi: 10.1109/JEDS.2020.2975220 https://t.co/34ZWW1P73Y https://t.co/hKNGErgo4I

#paper: Y. Liu, S. Yang and K. Sheng, "Design and Optimization of Vertical GaN PiN Diodes With Fluorine-Implanted Termination," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 241-250, 2020

doi: 10.1109/JEDS.2020.2975220https://t.co/34ZWW1P73Y pic.twitter.com/hKNGErgo4I

— Wladek Grabinski (@wladek60) March 6, 2020

from Twitter https://twitter.com/wladek60

March 06, 2020 at 09:17AM
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#paper: S. Mocevic et al., "Comparison and Discussion on Shortcircuit Protections for SiC MOSFET Modules: Desaturation vs. Rogowski Switch-Current Sensor," in IEEE Transactions on Industry Applications doi: 10.1109/TIA.2020.2972816 https://t.co/qYVwtxy2BF https://t.co/Z4oY9m6Dhl

#paper: S. Mocevic et al., "Comparison and Discussion on Shortcircuit Protections for SiC MOSFET Modules:
Desaturation vs. Rogowski Switch-Current Sensor," in IEEE Transactions on Industry Applications

doi: 10.1109/TIA.2020.2972816https://t.co/qYVwtxy2BF pic.twitter.com/Z4oY9m6Dhl

— Wladek Grabinski (@wladek60) March 5, 2020

from Twitter https://twitter.com/wladek60

March 05, 2020 at 03:59PM
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#paper: Q. Huo et al., "Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond," in IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 907-914, March 2020 doi: 10.1109/TED.2020.2964610 https://t.co/wEf5wGKzFv https://t.co/AGBu4ZUtVR

#paper: Q. Huo et al., "Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond," in IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 907-914, March 2020

doi: 10.1109/TED.2020.2964610 https://t.co/wEf5wGKzFv pic.twitter.com/AGBu4ZUtVR

— Wladek Grabinski (@wladek60) March 5, 2020

from Twitter https://twitter.com/wladek60

March 05, 2020 at 03:56PM
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#DATE 2020 in Grenoble replaced by a virtual conference that will be scheduled in the coming weeks https://t.co/vwd8IZqhPo #paper https://t.co/FNMBVw2LUl

#DATE 2020 in Grenoble
replaced by a virtual conference that will be scheduled in the coming weeks https://t.co/vwd8IZqhPo#paper pic.twitter.com/FNMBVw2LUl

— Wladek Grabinski (@wladek60) March 5, 2020

from Twitter https://twitter.com/wladek60

March 05, 2020 at 03:30PM
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#EDTM 2020 Conference going Virtual -The conference will be held as a Virtual conference with all presentations be posted online. -The pre-conference Tutorials and Short Courses on March 15th, 2020 is cancelled https://t.co/x9cC8kKu6D #paper https://t.co/M8C5uO6DQY

#EDTM 2020 Conference going Virtual
-The conference will be held as a Virtual conference with all presentations be posted online.
-The pre-conference Tutorials and Short Courses on March 15th, 2020 is cancelledhttps://t.co/x9cC8kKu6D#paper pic.twitter.com/M8C5uO6DQY

— Wladek Grabinski (@wladek60) March 5, 2020

from Twitter https://twitter.com/wladek60

March 05, 2020 at 03:24PM
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#paper: Krishna Pradeep, Patrick Scheer, Thierry Poiroux, André Juge and Gerard Ghibaudo; In-Wafer variability in FD-SOI MOSFETs: Detailed analysis and statistical modelling" Accepted Manuscript online 27 February 2020 by IOP Publishing Ltd https://t.co/rEjVnoRLuH https://t.co/V98FnxCpeo

#paper: Krishna Pradeep, Patrick Scheer, Thierry Poiroux, André Juge and Gerard Ghibaudo; In-Wafer variability in FD-SOI MOSFETs: Detailed analysis and statistical modelling" Accepted Manuscript online 27 February 2020 by IOP Publishing Ltdhttps://t.co/rEjVnoRLuH pic.twitter.com/V98FnxCpeo

— Wladek Grabinski (@wladek60) March 4, 2020

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March 04, 2020 at 02:51PM
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#paper #PhD: Michael Kollmitzer: Modeling of reverse current effects in trench-based smart power technologies. Gottfried Wilhelm Leibniz Universität, Diss., 2019, viii, 141 S. DOI: https://t.co/Uz3n1mRzzt https://t.co/mbBC0FR04m https://t.co/CVFveW4DXr

#paper #PhD: Michael Kollmitzer: Modeling of reverse current effects in trench-based smart power technologies. Gottfried Wilhelm Leibniz Universität, Diss., 2019, viii, 141 S.
DOI: https://t.co/Uz3n1mRzzthttps://t.co/mbBC0FR04m pic.twitter.com/CVFveW4DXr

— Wladek Grabinski (@wladek60) March 4, 2020

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March 04, 2020 at 02:34PM
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#paper: S. Rhee et al. "Extension of the DG Model to the Second-Order Quantum Correction for Analysis of the Single-Charge Effect in Sub-10-nm MOS Devices," in IEEE JEDS, vol. 8, pp. 213-222, 2020 doi: 10.1109/JEDS.2020.2971426 https://t.co/LhdoMi9pP3 https://t.co/YgUVWiBxlv

#paper: S. Rhee et al. "Extension of the DG Model to the Second-Order Quantum Correction for Analysis of the Single-Charge Effect in Sub-10-nm MOS Devices," in IEEE JEDS, vol. 8, pp. 213-222, 2020

doi: 10.1109/JEDS.2020.2971426 https://t.co/LhdoMi9pP3 pic.twitter.com/YgUVWiBxlv

— Wladek Grabinski (@wladek60) March 3, 2020

from Twitter https://twitter.com/wladek60

March 03, 2020 at 08:23AM
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“It is predicted that in 2030 transistors will be a sixth smaller" by Stephen Crosher https://t.co/ErClcb0e2R #paper https://t.co/PuTy7flK9O

“It is predicted that in 2030 transistors will be a sixth smaller"

by Stephen Crosher https://t.co/ErClcb0e2R#paper pic.twitter.com/PuTy7flK9O

— Wladek Grabinski (@wladek60) March 2, 2020

from Twitter https://twitter.com/wladek60

March 02, 2020 at 08:42AM
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#paper: A. Debnath, N. DasGupta and A. DasGupta, "Charge-Based Compact Model of Gate Leakage Current for AlInN/GaN and AlGaN/GaN HEMTs," in IEEE TED, vol. 67, no. 3, pp. 834-840, March 2020 doi: 10.1109/TED.2020.2965561 https://t.co/2HcKKjKOqE https://t.co/m6cKvAatEC

#paper: A. Debnath, N. DasGupta and A. DasGupta, "Charge-Based Compact Model of Gate Leakage Current for AlInN/GaN and AlGaN/GaN HEMTs," in IEEE TED, vol. 67, no. 3, pp. 834-840, March 2020

doi: 10.1109/TED.2020.2965561 https://t.co/2HcKKjKOqE pic.twitter.com/m6cKvAatEC

— Wladek Grabinski (@wladek60) March 2, 2020

from Twitter https://twitter.com/wladek60

March 02, 2020 at 08:29AM
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#paper: M. Albrecht, F. J. Klüpfel and T. Erlbacher, "An Iterative Surface Potential Algorithm Including Interface Traps for Compact Modeling of SiC-MOSFETs," in IEEE TED, vol. 67, no. 3, pp. 855-862, March 2020 doi: 10.1109/TED.2020.2967507 https://t.co/8fJMfKM9SP https://t.co/nlRiSs1Qf0

#paper: M. Albrecht, F. J. Klüpfel and T. Erlbacher, "An Iterative Surface Potential Algorithm Including Interface Traps for Compact Modeling of SiC-MOSFETs," in IEEE TED, vol. 67, no. 3, pp. 855-862, March 2020
doi: 10.1109/TED.2020.2967507 https://t.co/8fJMfKM9SP 

— Wladek Grabinski (@wladek60) February 28, 2020

from Twitter https://twitter.com/wladek60

February 28, 2020 at 06:12PM
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#paper: Thomas, S. Guiding the design of #negative-#capacitance #FETs. Nat Electron 3, 72 (2020). https://t.co/clMVy6syW9 https://t.co/zh8N3ynGIx https://t.co/s3KFFkQ8lT

#paper: Thomas, S. Guiding the design of #negative-#capacitance #FETs. Nat Electron 3, 72 (2020). https://t.co/clMVy6syW9 https://t.co/zh8N3ynGIx pic.twitter.com/s3KFFkQ8lT

— Wladek Grabinski (@wladek60) February 25, 2020

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February 25, 2020 at 02:57PM
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#Opensource licenses: What, which, and why https://t.co/kZlEUC5CQE https://t.co/G1WotNhQp8

#Opensource licenses: What, which, and why https://t.co/kZlEUC5CQE pic.twitter.com/G1WotNhQp8

— Wladek Grabinski (@wladek60) February 25, 2020

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February 25, 2020 at 09:42AM
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Fwd: IEEE-EDS Santa Clara Valley/San Francisco Chapter March Seminar

We are pleased to announce our monthly seminar for March

Wide Bandgap Devices Enabling High Power and High Frequency Electronics

Speaker: Professor Srabanti Chowdhury, Stanford University

Friday, March 13, 2020 at 11:45AM – 1PM

Texas Instruments Conference Center
2900 Semiconductor Dr, Building E, Santa Clara, CA 95051
FREE PIZZA PROVIDED

Register Here: https://www.surveymonkey.com/r/R7VKQ3M

Abstract:
We live in extremely exciting times, often identified as the age of the fourth industrial revolution. With electrification at every level, we are witnessing the most significant transformation of transportation since the internal combustion engine. Renewable energy is now a reality. IoT with the ever-expanding need for sensors and low power electronics is changing our lives dramatically. Robotics and autonomous vehicles are upon us. Both new and existing applications are demanding physical electronics solutions with new materials, devices and heterogeneous integration to drive these innovations to their full potential.

Wide-bandgap (WBG) semiconductors present a pathway to enable much of these electronics with higher efficiency and newer functionalities. Semiconductor devices with higher power density have unprecedented value in both power and high frequency electronics. Reducing conversion losses is not only critical for minimizing consumption of limited resources, it simultaneously enables new compact and reduced weight solutions, the basis for a new industry offering increased power conversion performance at reduced system cost. Equally importantly, GaN has opened the door to other ultra-wide bandgap materials such as Diamond, Aluminum Nitride and Gallium Oxide.

---

More information at the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

Subscribe or Invite your friends to sign up for our mailing list and get to hear about exciting electron-device relevant talks. We promise no spam and try to minimize email. You can unsubscribe easily.
http://site.ieee.org/scv-eds/subscribe/

[mos-ak] [Final Program] 2nd Latin America MOS-AK Workshop at LAEDC

2nd Latin America MOS-AK Workshop at LAEDC

(co-located with LAEDC /LASCAS)

Escazu, Costa Rica, February 25, 2020

<http://www.mos-ak.org/costa_rica_2020/>

Today, Professor Benjamin Iniguez URV, DEEEA, Tarragona, (SP) on behalf of the Extended MOS-AK TPC Committee will open 2nd consecutive Latin America MOS-AK Workshop

Scheduled, 2nd consecutive Latin America MOS-AK Workshop co-located with LAEDC /LASCAS aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

 

The MOS-AK workshop program is available online:

<http://www.mos-ak.org/costa_rica_2020/>

Venue:

Holiday Inn Hotel, 

Escazu, west of San José, 

Costa Rica

Online Registration is still open

(any related enquiries can be sent to register@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special Solid State Electronics issue on compact modeling 

W.Grabinski on behalf of International MOS-AK Committee

WG25022020

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Is #opensource software licensing broken? https://t.co/VBw6rf0nyi https://t.co/ECoreNRJR1

Is #opensource software licensing broken? https://t.co/VBw6rf0nyi pic.twitter.com/ECoreNRJR1

— Wladek Grabinski (@wladek60) February 24, 2020

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February 24, 2020 at 10:50AM
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#paper: R. Kotecha, G. Moreno, B. Mather and S. Narumanchi, "Modeling Needs for Power Semiconductor Devices and Power Electronics Systems," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 12.1.1-12.1.4. https://t.co/x6825AQzZ4 https://t.co/Cmrty3XJHJ

#paper: R. Kotecha, G. Moreno, B. Mather and S. Narumanchi, "Modeling Needs for Power Semiconductor Devices and Power Electronics Systems," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 12.1.1-12.1.4. https://t.co/x6825AQzZ4 pic.twitter.com/Cmrty3XJHJ

— Wladek Grabinski (@wladek60) February 21, 2020

from Twitter https://twitter.com/wladek60

February 21, 2020 at 02:41PM
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#paper: N. Chowdhury et al., "First Demonstration of a Self-Aligned #GaN p-FET," 2019 IEEE #IEDM, San Francisco, CA, USA, 2019, pp. 4.6.1-4.6.4. https://t.co/7u64T4nDe2 https://t.co/gOSilpZbW9

#paper: N. Chowdhury et al., "First Demonstration of a Self-Aligned #GaN p-FET," 2019 IEEE #IEDM, San Francisco, CA, USA, 2019, pp. 4.6.1-4.6.4. https://t.co/7u64T4nDe2 pic.twitter.com/gOSilpZbW9

— Wladek Grabinski (@wladek60) February 21, 2020

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February 21, 2020 at 02:40PM
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#paper: Z. Wu et al., "A physics-aware compact modeling framework for transistor aging in the entire bias space," 2019 IEEE IEDM, San Francisco, CA, USA, 2019, pp. 21.2.1-21.2.4. https://t.co/sF6okiUdAk https://t.co/bxo7NNAiiV

#paper: 

Z. Wu et al., "A physics-aware compact modeling framework for transistor aging in the entire bias space," 2019 IEEE IEDM, San Francisco, CA, USA, 2019, pp. 21.2.1-21.2.4. https://t.co/sF6okiUdAk

sEKV References:
[8] C Enz et al., SSCM, vol. 9, no. 3, 2017.
[9] A Mangla et al., MIXDES, 2011.

pic.twitter.com/bxo7NNAiiV

— Wladek Grabinski (@wladek60) February 21, 2020

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February 21, 2020 at 11:47AM
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Moving To #GAA #FETs https://t.co/17yYwyMDHI #paper https://t.co/eqPWdfdvEv

Moving To #GAA #FETs https://t.co/17yYwyMDHI #paper pic.twitter.com/eqPWdfdvEv

— Wladek Grabinski (@wladek60) February 21, 2020

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February 21, 2020 at 07:42AM
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Open-Gate Silicon JFET: Silicon Junction Field Effect Transistors are fabricated at 3IT.Nano | CMC Microsystems https://t.co/9Ip4MTCiGM #paper https://t.co/9qTuAU1TQl

Open-Gate Silicon JFET: Silicon Junction Field Effect Transistors are fabricated at 3IT.Nano | CMC Microsystems https://t.co/9Ip4MTCiGM#paper pic.twitter.com/9qTuAU1TQl

— Wladek Grabinski (@wladek60) February 20, 2020

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February 20, 2020 at 05:16PM
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#DATE 2020: Bridging the gap between #semiconductor technologies and architecture #design https://t.co/J8ThuGc7Rv #paper https://t.co/UJQEYSofLG

#DATE 2020: Bridging the gap between #semiconductor technologies and architecture #design https://t.co/J8ThuGc7Rv #paper pic.twitter.com/UJQEYSofLG

— Wladek Grabinski (@wladek60) February 20, 2020

from Twitter https://twitter.com/wladek60

February 20, 2020 at 03:04PM
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