P. Kushwaha et al., "Characterization and Modeling of Flicker #Noise in #FinFETs at Advanced Technology Node," in IEEE Electron Device Letters. doi: 10.1109/LED.2019.2911614 https://t.co/RuzIYlIOiL #paper https://t.co/y7lpjHI02W

P. Kushwaha et al., "Characterization and Modeling of Flicker #Noise in #FinFETs at Advanced Technology Node," in IEEE Electron Device Letters.
doi: 10.1109/LED.2019.2911614 https://t.co/RuzIYlIOiL #paper pic.twitter.com/y7lpjHI02W

— Wladek Grabinski (@wladek60) April 29, 2019

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April 29, 2019 at 09:32AM
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A Compact Model for Border Traps in Lateral MOS Devices with Large Channel Resistance https://t.co/p9sOA4A8Ee #paper

A Compact Model for Border Traps in Lateral MOS Devices with Large Channel Resistance https://t.co/p9sOA4A8Ee #paper

— Wladek Grabinski (@wladek60) April 26, 2019

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April 26, 2019 at 09:14PM
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A Quick #TSMC 2019 Tech Symposium Overview #FinFET https://t.co/NzINOJTciz #paper

A Quick #TSMC 2019 Tech Symposium Overview #FinFET https://t.co/NzINOJTciz #paper

— Wladek Grabinski (@wladek60) April 26, 2019

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April 26, 2019 at 02:29PM
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H. Cortes-Ordonez, S. Jacob, F. Mohamed, G. Ghibaudo and B. Iniguez, "Analysis and Compact Modeling of Gate Capacitance in Organic Thin-Film Transistors," in IEEE Transactions on Electron Devices, vol. 66, no. 5, pp. 2370-2374, May 2019. https://t.co/IHtWBBiqiI #paper https://t.co/Ryp6FJ6TlS

H. Cortes-Ordonez, S. Jacob, F. Mohamed, G. Ghibaudo and B. Iniguez, "Analysis and Compact Modeling of Gate Capacitance in Organic Thin-Film Transistors," in IEEE Transactions on Electron Devices, vol. 66, no. 5, pp. 2370-2374, May 2019.
https://t.co/IHtWBBiqiI #paper pic.twitter.com/Ryp6FJ6TlS

— Wladek Grabinski (@wladek60) April 25, 2019

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April 25, 2019 at 09:34PM
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#Emerging #memories https://t.co/Iv50OpzJGO #paper

#Emerging #memories https://t.co/Iv50OpzJGO #paper

— Wladek Grabinski (@wladek60) April 25, 2019

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April 25, 2019 at 07:20AM
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#TSMC Steps Through 7, 6, 5, #Moore https://t.co/qauTuVuRNu #paper

#TSMC Steps Through 7, 6, 5, #Moore https://t.co/qauTuVuRNu #paper

— Wladek Grabinski (@wladek60) April 24, 2019

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April 24, 2019 at 07:01PM
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Controlling #IC Manufacturing #Processes For #Yield https://t.co/Jkaagd6fcH #paper

Controlling #IC Manufacturing #Processes For #Yield https://t.co/Jkaagd6fcH #paper

— Wladek Grabinski (@wladek60) April 24, 2019

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April 24, 2019 at 06:57PM
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Silicon Valley #SOI Symposium a Huge Success. Key #Takeaways (Part 1) Here. https://t.co/gDG4fZGnC3 #paper

Silicon Valley #SOI Symposium a Huge Success. Key #Takeaways (Part 1) Here. https://t.co/gDG4fZGnC3 #paper

— Wladek Grabinski (@wladek60) April 24, 2019

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April 24, 2019 at 07:18AM
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Changes in the Editorial Board of the IEEE Transactions on Electron Devices (#TED)” https://t.co/IdvKWuxOyh #paper https://t.co/JslqPEuBE6

Changes in the Editorial Board of the IEEE Transactions on Electron Devices (#TED)” https://t.co/IdvKWuxOyh #paper pic.twitter.com/JslqPEuBE6

— Wladek Grabinski (@wladek60) April 23, 2019

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April 23, 2019 at 08:04PM
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#UK grant for #opensource #healthcare https://t.co/3Nvmv3dz2a https://t.co/PoZhtCfryo

#UK grant for #opensource #healthcare https://t.co/3Nvmv3dz2a pic.twitter.com/PoZhtCfryo

— Wladek Grabinski (@wladek60) April 21, 2019

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April 21, 2019 at 07:56PM
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Is #ETHZ’s genetically engineered ‘biological dual-core processor’ actually a pair of gates? https://t.co/4swqZuKfk6 #paper https://t.co/OMlQyV8sTs

Is #ETHZ’s genetically engineered ‘biological dual-core processor’ actually a pair of gates? https://t.co/4swqZuKfk6 #paper pic.twitter.com/OMlQyV8sTs

— Wladek Grabinski (@wladek60) April 17, 2019

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April 17, 2019 at 10:10PM
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#MEMS research is better #together #Japan https://t.co/chDClsOcjZ #paper https://t.co/7zUt4UisGI

#MEMS research is better #together #Japan https://t.co/chDClsOcjZ #paper pic.twitter.com/7zUt4UisGI

— Wladek Grabinski (@wladek60) April 17, 2019

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April 17, 2019 at 09:39PM
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W. Wang, P. Yu and Y. Jiang, "#Compact #Model for Digital Circuits Operating Near Threshold in Deep-Submicrometer MOSFET," in IEEE TED doi: 10.1109/TED.2019.2905895 https://t.co/ST4J8u2pRY https://t.co/3bYTnxKi3c

W. Wang, P. Yu and Y. Jiang, "#Compact #Model for Digital Circuits Operating Near Threshold in Deep-Submicrometer MOSFET," in IEEE TED
doi: 10.1109/TED.2019.2905895 https://t.co/ST4J8u2pRY pic.twitter.com/3bYTnxKi3c

— Wladek Grabinski (@wladek60) April 17, 2019

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Symposium on Schottky Barrier MOS devices

“Towards neuromorphic and quantum computing applications” 

October 4, 2019, Paris (F)

organized by EDS French Chapter & Universite Paris-Sud

A symposium on Schottky Barrier MOS (SB-MOS) devices is planned for October 4th at the new Center for Nanoscience and Nanotechnology laboratory in Palaiseau, France. This is the third meeting of an enthusiastic group of Schottky barrier researchers and this year it is sponsored by LabexNanoSaclay, the IEED EDS French chapter, the Robert Bosch GmbH and Silvaco Inc.

This year the theme of the symposium is “Towards neuromorphic and quantum computing applications” organized by Dr. Laurie Calvet (C2N, Palaiseau, France), Dr. Francesca Chiodi (C2N, Palaiseau, France), Dr. Mireille Mouis (IMEP-LAHC, Grenoble INP, France) and Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany) and the staff at the Centre of Nanoscience and Nanotechnology at the Université Paris-Sud. 

The symposium starts on October 4th at 9:00 am and the following speakers have confirmed their invitations: Prof. Benjamin Iniguez (DEEEA, Universitaet Rovira I Virgili), Dr. Laurie E. Calvet (C2N, CNRS-Université Paris-Sud), Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany), Dr. David Green / Dr. Ahmed Nejim (Silvaco Inc.), Dr. John Snyder (JCAP, LLC), Dr. Francesca Chiodi (C2N, CNRS-Université Paris-Sud), Dr. François Lefloch (CEA, Grenoble), Dr. Fabrice Nemouchi (CEA, Grenoble).

Restoring An #HP4276A LCZ Meter From The 1980s https://t.co/K9LM1c5Ao0 #paper

Restoring An #HP4276A LCZ Meter From The 1980s https://t.co/K9LM1c5Ao0 #paper

— Wladek Grabinski (@wladek60) April 7, 2019

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April 07, 2019 at 05:10PM
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First #opensource #MIPS code is released https://t.co/0NbQasWuVx

First #opensource #MIPS code is released https://t.co/0NbQasWuVx

— Wladek Grabinski (@wladek60) April 6, 2019

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April 06, 2019 at 10:19PM
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2019 CAD-TFT Workshop in Tarragona (Spain)

2019 International Workshop on

Computer Aided Design of Thin-Film Transistors (CAD-TFT)

University Rovira i Virgili, Tarragona (Catalonia) Spain

July 8-10, 2019

The 2019 CAD-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling and to promote research on CAD techniques at all levels (TCAD, compact modelling, circuit & system design) for TFT technologies. It is also intended to promote the training of students, young researchers and engineers and to build international, academic-industry, and cross-level collaborations to evoke new applications of TFT technologies. The workshop will technically be co-sponsored by the IEEE EDS Compact Modeling Technical Committee, in joint collaboration with the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV) and Silvaco Europe Ltd. An EDS Mini-Colloquium will take place on July 8. 

The chair of the 2019 CAD-TFT Workshop and the EDS Mini-Colloquium is Prof. Benjamin Iñiguez, from URV.

 

A partial list of the areas of interest includes:

· Physics of TFTs and operating principles

· Compact TFT device models for circuit simulation

· Model implementation and circuit analysis techniques

· Model parameter extraction techniques

· TFT design for displays and emerging applications

█ Abstract Submission Deadline: May 1, 2019

Please note, abstracts will be considered for the conference even after the official submission deadline.

Prospective participants should email a no-more-than 100-word abstract to: benjamin.iniguez@urv.cat

Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.

Tarragona is one of the most  important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

S. Hong, "Compact Charge Modeling of Double-Gate MOSFETs Considering the Density-Gradient Equation," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 409-416, 2019. doi: 10.1109/JEDS.2019.2903854 https://t.co/qaoEggYw9v #paper https://t.co/re4irM7K0C

S. Hong, "Compact Charge Modeling of Double-Gate MOSFETs Considering the Density-Gradient Equation," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 409-416, 2019. doi: 10.1109/JEDS.2019.2903854 https://t.co/qaoEggYw9v #paper pic.twitter.com/re4irM7K0C

— Wladek Grabinski (@wladek60) April 3, 2019

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April 03, 2019 at 11:22PM
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Y. Cao, W. Zhang, J. Fu, Q. Wang, L. Liu and A. Guo, "A Complete Small-Signal MOSFET Model and Parameter Extraction Technique for Millimeter Wave Applications," in IEEE JEDS, vol. 7, pp. 398-403, 2019. doi: 10.1109/JEDS.2019.2900202 https://t.co/boPOK6la6Y #paper https://t.co/GxAhkKRx5K

Y. Cao, W. Zhang, J. Fu, Q. Wang, L. Liu and A. Guo, "A Complete Small-Signal MOSFET Model and Parameter Extraction Technique for Millimeter Wave Applications," in IEEE JEDS, vol. 7, pp. 398-403, 2019.
doi: 10.1109/JEDS.2019.2900202 https://t.co/boPOK6la6Y #paper pic.twitter.com/GxAhkKRx5K

— Wladek Grabinski (@wladek60) April 1, 2019

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April 01, 2019 at 09:42PM
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#Switzerland has become the 27th European country to join the European High Performance Computing Joint Undertaking #EuroHPC https://t.co/iv6GlZiLtW #paper https://t.co/6yfKdAjoQN

#Switzerland has become the 27th European country to join the European High Performance Computing Joint Undertaking #EuroHPC https://t.co/iv6GlZiLtW #paper pic.twitter.com/6yfKdAjoQN

— Wladek Grabinski (@wladek60) March 27, 2019

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March 28, 2019 at 12:06AM
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An EU-funded project has fostered in-depth dialogue between #Europe and #Russia on stepping up #scientific #collaboration https://t.co/XoFy3YYbGF #paper https://t.co/1ME2dBFS8W

An EU-funded project has fostered in-depth dialogue between #Europe and #Russia on stepping up #scientific #collaboration https://t.co/XoFy3YYbGF #paper pic.twitter.com/1ME2dBFS8W

— Wladek Grabinski (@wladek60) March 27, 2019

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March 27, 2019 at 11:52PM
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Moore's Law Ending? No Problem. how to stop worrying and love the end of Moore's Law https://t.co/taDtZ1uHt2 #paper

Moore's Law Ending? No Problem. how to stop worrying and love the end of Moore's Law https://t.co/taDtZ1uHt2 #paper

— Wladek Grabinski (@wladek60) March 27, 2019

from Twitter https://twitter.com/wladek60

March 27, 2019 at 09:03PM
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28nm #FDSOI #Analog and #RF Figures of Merit at N2 #Cryogenic Temperatures https://t.co/bAjD2Z8OT1 #paper https://t.co/1zfIXBF0vh

28nm #FDSOI #Analog and #RF Figures of Merit at N2 #Cryogenic Temperatures https://t.co/bAjD2Z8OT1 #paper pic.twitter.com/1zfIXBF0vh

— Wladek Grabinski (@wladek60) March 26, 2019

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March 26, 2019 at 10:42PM
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#ARM extends IP support to #18nm #FDSOI https://t.co/Nn8ftvcrOP #model https://t.co/u168ghX5C8

#ARM extends IP support to #18nm #FDSOI https://t.co/Nn8ftvcrOP #model pic.twitter.com/u168ghX5C8

— Wladek Grabinski (@wladek60) March 25, 2019

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March 25, 2019 at 11:01PM
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#SOI Silicon Valley #Symposium 2019 https://t.co/SoaSfIy83W #paper https://t.co/OM6toA3GTO

#SOI Silicon Valley #Symposium 2019 https://t.co/SoaSfIy83W #paper pic.twitter.com/OM6toA3GTO

— Wladek Grabinski (@wladek60) March 20, 2019

from Twitter https://twitter.com/wladek60

March 21, 2019 at 12:28AM
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The #World Might Be Better Off #Without #College for Everyone https://t.co/9JgJ5e7BPI #paper https://t.co/lQNNUmCmiA

The #World Might Be Better Off #Without #College for Everyone https://t.co/9JgJ5e7BPI #paper pic.twitter.com/lQNNUmCmiA

— Wladek Grabinski (@wladek60) March 20, 2019

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March 21, 2019 at 12:14AM
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K.U. Giering et al., "NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling," in IEEE Transactions on Electron Devices, vol. 66, no. 4, pp. 1662-1668, April 2019. doi: 10.1109/TED.2019.2901907 https://t.co/XqBHjwCXXS #paper https://t.co/4oIN7ev19B

K.U. Giering et al., "NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling," in IEEE Transactions on Electron Devices, vol. 66, no. 4, pp. 1662-1668, April 2019.
doi: 10.1109/TED.2019.2901907 https://t.co/XqBHjwCXXS #paper pic.twitter.com/4oIN7ev19B

— Wladek Grabinski (@wladek60) March 19, 2019

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March 19, 2019 at 10:44PM
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Microelectronic conferences #Chip in #Sampa 2019 in São Paulo, SP, Brazil between August 26 to 30, 2019 #SBMicro https://t.co/AwxOarqtAl #paper https://t.co/5Af1tL5q3g

Microelectronic conferences #Chip in #Sampa 2019 in São Paulo, SP, Brazil between August 26 to 30, 2019 #SBMicro https://t.co/AwxOarqtAl #paper pic.twitter.com/5Af1tL5q3g

— Wladek Grabinski (@wladek60) March 18, 2019

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March 18, 2019 at 08:06PM
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[mos-ak] [2nd Announcement and C4P] 4th Sino MOS-AK Workshop, Chengdu (CN) June 20-22, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

4th Sino MOS-AK Workshop

Chengdu, China June 20-22, 2019

Together with local UESTC organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 4th Sino MOS-AK Workshop which will be organized at University of Electronic Science and Technology of China (电子科技大学) Chengdu, China between June 20-22, 2019 .

The MOS-AK Workshop in Chengdu, China, is dedicated to advanced electronic and photonic devices. MOS-AK Modeling Association has more than 20 years history of enabling compact/SPICE modeling R&D exchange, please refer to MOS-AK website. With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/optics. With this background, the workshop aims to strengthen a network and discussion forum among experts in the field, provide a forum for the presentation and discussion of the leading edge research and development results of Compact Modeling, Characterization and Simulation techniques for advanced devices, circuits and technologies. Modeling and validation technique of all solid-state devices, including, Si, III-V, power, nanoscale electronic structures and other related new devices are within the scope of the conference. The forefront theme of MOS-AK is "Bridge of Process Technology and Integrated Circuits & Systems Design". 

The MOS-AK Workshop will be held between June 21-22, 2019 at University of Electronic Science and Technology of China (UESTC) in Chengdu, China. The main goal is to exchange compact modeling (CM) related know-how and promote modeling technique to support semiconductor industry. In addition to oral presentations, distinguished experts in the modeling field will be invited to deliver keynote speeches on significant trends, advancements and applications in compact/SPICE modeling domain. On June 20, 2019 we also offer 1day training course related to "SiGe HBTs for mm-Wave Systems Applications" held by Dr. Andreas Pawlak and Dr. Wojciech Debski. In addition, a national students design competition based on GaN HEMT on Si process (OMMIC GaN D01GH) will be also announced. Winners, either single person or team will be awarded with free tapeout, bonus & issued certificate supported by Yifeng-UESTC. 

We welcome industrial partners to show their latest equipment, tools and all other related to the compact/SPICE modeling. After workshop, extremely excellent papers will be selected and recommended for publication in the renowned Journal such as Weily's International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (SCI Index) or International Journal of High Speed Electronics and Systems (EI Index).

Venue:

University of Electronic Science and Technology of China

电子科技大学

Chengdu, China

Important Dates:

Call for Papers - Dec. 2018

2nd Announcement - March 2019

Final Workshop Program - May 2019

MOS-AK Workshop: June 20-22, 2019

Paper Submission deadline: May 20, 2019 (Monday) 

Submission address: yyuan@std.uestc.edu.cn

Notification of Acceptance:  June 3, 2019 (Monday)

Submission of final manuscript: June 10, 2019 (Monday)

Online Registration (to be open in Apr.2019 any related enquiries can be sent to Workshop Secretary: Yuan Yao (Mobile:13086679508))

On the behalf of the Organizing Committee:

Yuhang Xu, UESTC 电子科技大学

Wladek Grabinski, MOS-AK  (EU)

International R&D Adviser :

Min Zhang, XMOD

Advisory Committee:

Yue Hao, Xidian University

Jose Pedro, T-MTT Editor

Yogesh Chauhan, T-ED Editor

WG14032019 

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[mos-ak] [press note] 2nd MOS-AK India Conference at IIT Hyderabad Feb. 25-27, 2019

2019 IEEE International Conference on Modeling of Systems Circuits and Devices

Organised by Joint Chapter of CAS /ED Societies, IEEE Hyderabad Section

2nd MOS-AK India Conference (IEEE Conference #45395)

Venue: IIT Hyderabad February 25-27, 2019

The MOS-AK Compact Modeling Association, a global standardization forum for semiconductor device models, held its consecutive 2nd International IEEE MOS-AK India Conference 2019 between February 25-27, 2019 at the IIT Hyderabad. The 2nd International IEEE MOS-AK India Conference 2019 is the results of join, collaborative effort. The conference organization would not be possible without direct involvements and financial support provided directly by Collage and IIT Hyderabad as well as the MOS-AK distinguished industrial sponsors including: ams semiconductors, Rhode and Schwarz, Keysight, Synergy, Synopsys, Xilinx and SCL. The MOS-AK India Conference has  also drawn attention of the Joint Chapter of the CAS and EDS Societies of the IEEE Hyderabad Section which provided direct technical program cosponsorship. The Indian Electronic Semiconductor Association (IESA) as well as Swissnex India have provide pronounced dissemination support.

Inauguration session of 2nd International IEEE MOS-AK India Conference 2019 has been chaired by Prof. Mohammed Arifuddin Sohel, MJ College Hyderabad, who welcomed all MOS-AK participants and invited prominent guests Surinder Singh, Director, SCL;  Sebasties Hug, CEO and Consul General of Swissnex;  Sumohan Chenapayya, Dean R&D, IIT Hyderabad;  V. Hanuma Sai, Director, ams semiconductors India Pvt. Ltd.;  N. Venkatesh, Chair, IEEE Hyderabad Section;  Wladek Grabinski, MOS AK (EU);  P.A. Govindacharyulu, General Co Chair, MOS AK India 2019  to open  the 2nd MOS-AK/India Conference.

The MOS-AK India Conference program has been organized as three days scientific R&D event covering recent advances into the technology TCAD simulations, compact/SPICE modeling as well as the device level analog/RF and digital IC designs. The internationally renowned academic and industrial speakers and presenters have delivered 4 tutorial lectures [1-4], 7 keynote talks [5-11], 2 plenary talks [12-13] as well as 22 regular research papers. The MOS-AK Association is an open research forum adequately supporting all R&D activities. An open panel discussion was organized to review challenges and opportunities for women in engineering (WIE) [14]. The MOS-AK speakers shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in response to the dynamically evolving semiconductor industry and academic R&D efforts. The event featured advanced technical presentations covering compact model development, implementation, and deployment. Presented original unpublished works in all the topics related to the compact/SPICE modeling and its Verilog-A standardization will be submitted for further publication. The conference proceedings will be submitted to IEEE Explore. Best MOS-AK/India papers has been selected and awarded: Gold leaf [15], Silver leaf [16] and Bronze leaf [17] certificates, accordingly. Highest ranked paper authors from regular submission will be invited to extend their R&D contribution in the form of a book chapters in a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoter of MOS-AK/India 2019 Conference. These R&D topics have also received attention of local media and press [18-21]. For more information about each of the R&D contributions, go online to 2nd MOS-AK/India Conference

Photo: All the MOS-AK/India Conference participants at IIT Hyderabad

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses arround the globe thru 2019 year, including:

• 4th Sino MOS-AK Workshop, Chengdu (CN) June 2019
• 17th MOS-AK at ESSDERC/ESSCIRC, Krakow (PL), Sept. 2019
• 12th International MOS-AK Workshop, Silicon Valley (US) Dec. 2019
• 3rd MOS-AK India Conference, Hyderabad, Feb. 2020

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

Tutorials:

[1] Dr. Charvaka Duvvury iT2 Technologies (USA) ESD on-chip protection design 

[2] Dr. Wladek Grabinski MOS-AK (EU) Verilog-A Standardization

[3] Weronika Zubrzycka, AGH, (PL) Radiation effect and Radiation hardening in devices 

[4] Prof. Roberto Murphy, INOE (MX) Characterization of Semiconductor Devices in the High Frequency Regime

Keynote Talks: 

[5] Prof. Yogesh Singh Chauhan, IIT Kanpur (IN) Negative Capacitance Transistors - Modeling, Simulation and Processor Performance

[6] Dr. Surinder Singh, Semiconductor Labs, Chandigarh  (IN), Chandigarh Research at SCL

[7] Weronika Zubrazycka, AGH, (PL) Radiation Effects on Circuits for Space and High-Energy Physics Applications - A case study 

[8] Madabusi Govindrajan, GLOBALFOUNDRIES, Bangalore (IN)  Challenges for RF modeling in the connected era 

[9] Dr. Usha Gogineni, Maxim Semiconductors (IN)  Compact Models for Analog and Mixed Signal Design 

[10] Prof. Santanu Mahapatra, IISc, Bangalore (IN)  Atom-to-Circuit modeling technique for emerging nanomaterial based MOSFETs 

[11] Prof. Gilson Wirth, UFRGS (BR) (Webinar) Charge Trapping Phenomena in MOSFETS: From Noise to Bias Temperature Instability 

Plenary Talks: 

[12] Prof. Jaijeet Roychowdhury, UC, Berkeley, USA Well-Posed Compact Modeling 

[13] Dr. Ehrenfried Seebacher, ams (A) Compact Modeling for Industrial Applications 

Panel Discussion: 

[14] Dr. G. Uma Devi, Director, NRSC, (IN): Challenges and opportunities for Women in Engineering (WIE). 

Best papers awards:

[15] Chithra and Nagendra Krishnapura, "Modeling Techniques for Faster Verification of a Time to Digital Converter System-on-Chip Design"

[16] Mohit Ganeriwala, Enrique Marin, Francisco Ruiz and Nihar Mohapatra," A Compact Charge and Surface Potential Model for III-V Quadruple-Gate FETs With Square Geometry"

[17] Suprava Dey, Tara Prasanna Dash, Chinmay Kumar Maiti, Jhansirani Jena, Eleena Mohapatra and Sanghamitra Das," Performance Evaluation of Gate-All-Around Si Nanowire Transistors with SiGe Strain engineering"

Headlines: 

[18] "Swiss interest in India's energy and tech fields" Date: Feb. 27,2019 Publication: The Hindu Edition: Hyderabad

[19] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices" India Education diary  Edition: Online: Prof. Sushmee Badhulika 

[19] Indo-Swiss collaboration needed in education" Date: Feb. 27,2019 Publication: The New Indian express, Edition: Hyderabad

[20] "Switzerland looking forward to stronger ties with Telangana" Feb. 27,2019   Publication: Telangana Today, Edition:  Hyderabad

[21] "IIT Hyderabad hosts MOS-AK India 2019 International Conference on Modeling of Systems Circuits and Devices " Date: Feb. 27,2019 Publication: Andhra Jyothi Edition: Hyderabad pp:3

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B. Tiwari et al., "Oxide TFT Rectifiers on Flexible Substrates Operating at NFC Frequency Range," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 329-334, 2019. doi: 10.1109/JEDS.2019.2897642 https://t.co/cizT5Ek6Uy #paper

B. Tiwari et al., "Oxide TFT Rectifiers on Flexible Substrates Operating at NFC Frequency Range," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 329-334, 2019.
doi: 10.1109/JEDS.2019.2897642 https://t.co/cizT5Ek6Uy #paper

— Wladek Grabinski (@wladek60) March 11, 2019

from Twitter https://twitter.com/wladek60

March 11, 2019 at 08:38PM
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EspoTek Labrador: A small, portable, USB-connected electronics lab-on-a-board that includes an oscilloscope, waveform generator, power supply, logic analyzer, and multimeter.” https://t.co/KjhalAi080 #modeling https://t.co/HwU5AkhWZD

EspoTek Labrador: A small, portable, USB-connected electronics lab-on-a-board that includes an oscilloscope, waveform generator, power supply, logic analyzer, and multimeter.” https://t.co/KjhalAi080 #modeling pic.twitter.com/HwU5AkhWZD

— Wladek Grabinski (@wladek60) March 10, 2019

from Twitter https://twitter.com/wladek60

March 10, 2019 at 03:06PM
via IFTTT