[mos-ak] C4P MOS-AK/GSA Workshop in Washington DC on Dec. 7 2011

C4P MOS-AK/GSA Workshop in Washington DC on Dec. 7 2011
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http://www.mos-ak.org/washington_dc/
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Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop in
Washington DC on Dec. 7 2011

The MOS-AK/GSA Workshop is HiTech forum to discuss the frontiers of
the electron devices modeling with emphasis on simulation-aware
models. Original papers presenting new developments and advances in
the compact/spice modeling and its Verilog-A standardization are
solicited. The main topics of the workshop are: (but are not limited
to):
* Compact Modeling (CM) of the electron devices
* VHDL-AMS/Verilog-A for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Transistor Level IC support
* Nanoscale CMOS devices and circuits
* Reliability and thermal management of electron devices
* Technology R&D, DFY, DFT and IC designs
* Foundry/Fabless interface strategies

The terms of participation:
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Authors are asked to submit a short (~200words) abstract using on-
line
submission form by OCT.30 http://www.mos-ak.org/washington_dc
Intending authors should also note the following deadlines:
* Announcement and Call for Papers - Oct 2011
* on-line abstract submission deadline - OCT.30, 2011
* Final Workshop Program - Nov. 2011
* MOS-AK/GSA Workshop - Dec. 7, 2011
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Further details and updates and on-line workshop registration:
http://www.mos-ak.org/washington_dc
Email contact: washington_dc@mos-ak.org
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Institute of Electron Technology (ITE Warsaw, PL) - IC Design

IBM Seeking:

For Analog/Mixed Signal Predictive Device, Process Simulation (TCAD) Engineer
[check: http://bit.ly/ny9DkU] #jobs #vermont

Nonvolatile Memory Standard CMOS Process

A Japanese research group developed a technology to realize a nonvolatile memory by using only a standard CMOS process for logic chips. [more]

8th International Conference on Devices, Circuits and Systems (ICCDCS)

ICCDCS is an IEEE-EDS technically sponsored international conference biannually held since its first edition (Caracas, 1995) at different locations within the Caribbean basin. Over time this conference has acquired a prestigious position as the outstanding international IEEE conference dealing with Electron Devices and Circuits and Systems which takes place within the Latin American Region.

Its main objective is to serve as a significant meeting point and technical forum to initiate, renew and maintain direct personal relations aimed at sharing relevant technical know-how among Latin American and rest-of-the-world professionals involved in the disciplines that it covers. Industry, Universities and R&D Institutions are invited to participate. English is the official working language of the Conference, although Spanish and Portuguese are also freely used in informal communications.

Prospective authors are invited to submit contributions for oral presentations to be reviewed by the Technical Program Committee. They should deal with new results, relevant ideas or innovations that advance the state-of-the-art in the areas of the Technical Program. Topics may span from basic theory to industrial applications, research, development, design, technology and applications of electron devices, analysis, design, and practical implementation of circuits, and their application to power electronics, telecommunications and instrumentation. 

Location: 

The ICCDCS'12 will be held on Playa del Carmen, México, from March 14 through March 17, 2012

You can download the pdf version of the Call for Papers here.

[Internship] Modeling of GaN Power Transistors for IC Design

Internship framework: At the heart of the MINATEC innovation campus, Leti institute is one of the most important R&D laboratories in Europe in the field of microelectronics and nanotechnologies. Within the Alternative Energies and Atomic Energy Commission, CEA-Leti is developing GaN-based technologies and power devices for energy conversion in different industrial fields (energy management, automotive electronics, electric car). In order to design and simulate integrated circuits, it is mandatory to develop electro-thermal models of power transistors.  

Work description: The aim of the internship is to develop a specific model for GaN-based high electron mobility transistors (HEMTs). This wide bandgap semiconductor is one of the most promising for power electronics and is currently the subject of extensive research. This internship will take place in the Simulation and Modeling laboratory (LSM) of the Silicon Components Division (DCOS).  

This internship is divided into four parts:

1. Understanding of physical phenomena (electrical, thermal) in power HEMT transistors and analysis of existing models
2. TCAD numerical simulations of devices. 
3. Compact modeling of transistors starting from previous studies on silicon carbide (SiC) transistors. 
4. Depending on availability, static and pulsed measurements on GaN transistors and extraction of model parameters.  

Host Institution
Direction/Département/Service/Laboratoire CEA-LETI – DRT/DCOS/SCME/LSM
Postal address
CEA/GRENOBLE, MINATEC Campus,
17 rue des Martyrs 38054 Grenoble CEDEX 9
France  

Technical Supervisor 
Patrick MARTIN
Phone: 04 38 78 67 05

SPICE3: Prehistory, The Dark Age and Renaissance

[more: Paolo Nenzi, "ngSpice - a GNU standardization perspective" at MOS-AK/Helsinki]