Accurately simulate an LED

Accurately simulate an LED: " View as PDF Read More Design IdeasSolid-state-lighting applicatio..."

SEMI urges less bureaucratic approach to EU research funding

SEMI urges less bureaucratic approach to EU research funding: "San Jose-based manufacturing organization SEMI is advocating for a simplifica..."

The Nobel Prize in Physics 2010 (graphene)

The Royal Swedish Academy of Sciences has decided to award the Nobel Prize in Physics for 2010 to Andre Geim and Konstantin Novoselov, both at University of Manchester, UK “for groundbreaking experiments regarding the two-dimensional material graphene”.


Andre Geim, Dutch citizen. Born 1958 in Sochi, Russia. Ph.D. 1987 from Institute of Solid State Physics, Russian Academy of Sciences, Chernogolovka, Russia. Director of Manchester Centre for Meso-science & Nanotechnology, Langworthy Professor of Physics and Royal Society 2010 Anniversary Research Professor, University of Manchester, UK. 
Konstantin Novoselov, Brittish and Russian citizen. Born 1974 in Nizhny Tagil, Russia. Ph.D. 2004 from Radboud University Nijmegen, The Netherlands. Professor and Royal Society Research Fellow, University of Manchester, UK.

Read the press release...

AWR Announces New PDK for Cree GaN HEMT MMIC Foundry

The Cree GaN HEMT MMIC process features high power density (4-6 watts/mm) transistors, slot vias, and high reliability (up to 225ºC operating channel temperatures), as well as scalable transistors. [more]

[mos-ak] MOS-AK/GSA Seville Workshop on-line Publications

MOS-AK/GSA Seville workshop on-line publications are available:
http://www.mos-ak.org/seville/

More that 50 registered participants followed 2 keynote invited
presentations, 7 technical compact modeling talks as well as 15 poster
presentation at the MOS-AK/GSA ESSEDERC/ESSCIRC Compact Modeling
Workshop. I would like to thank all MOS-AK/GSA speakers and poster
presenters for sharing their compact modeling competence, R&D
experience and delivering valuable MOS-AK/GSA presentations. I am
sure, that our modeling event in Seville was beneficial to all MOS-AK
Workshop attendees.

Please note that as a result of post workshop discussion, the Dolphin
Verilog-A Compact Model Coding Whitepaper is available for direct
download:
http://www.dolphin-integration.com/medal/smash/notes/Verilog_A_Compact_Model_Coding_Whitepaper.pdf

Organization of our modeling event would not be possible without our
generous sponsors: Cascade Microtech and X-FAB Semiconductor Foundries
as well as the IEEE EDS, technical co-sponsor. I also would like to
personally acknowledge local ESSDERC/ESSCIRC organizers, in
particular, Professors Manuel Delgado Restituto, Andrés Godoy, the
ESSDERC/ESSCIRC Tutorials & Workshops Chairs for their dedication,
commitment. My very special 'thank you' goes also to Susana Eiroa for
her assistance and providing smooth workshop logistics.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
––––––––––––––––––––––––––––––––––
MOS-AK/Seville on-line publications <http://mos-ak.org/seville>
MOS-AK/California (Dec.2010; IEDM time frame)
IWCM at ASP-DAC in Yokohama Jan.2011 (with MOS-AK Support)
MOS-AK/Paris at LIP6 (March/April 2011)
MIXDES in Gliwice June 16-18, 2011 (with MOS-AK Session)
MOS-AK/Helsinki Sept.16, 2011 (ESSDERC time frame)
––––––––––––––––––––––––––––––––––

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CEA-Leti Makes a R&D 20nm Fully Depleted SOI Process available through CMP

Grenoble, FRANCE, and Tokyo, JAPAN, October 1st , 2010, CEA-Leti and CMP (Circuits Multi Projets®) announced during the FDSOI Workshop at Tokyo University the launch of an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process, opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+ network that gathers the main European academic partners on SOI.

The basis of the Fully Depleted SOI 20nm technology offer will be the following:

• CMOS transistors with an undoped channel and a silicon film thickness of 6nm
• High-k / Metal Gate stack
• Single threshold voltage (Vth) n- and p-MOSFET with balanced Vth of ±0.4V
• Associated Design Kit, including SPICE model (Verilog-A language), model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics
• Design Kit documentation

CMP Press Contacts:

Bernard Courtois +33 4 76 57 46 15

Kholdoun Torki +33 4 76 57 47 63

Shipments of silicon for semiconductor manufacturing raise more than 23%

I copy part of a post from EDN:

Shipments of silicon for semiconductor manufacturing in 2010 will grow by 23.6% year-over-year, reaching 8.9 billion total square inches, according to iSuppli estimates.

Global silicon shipments in terms of square inches are bouncing back in 2010, after suffering like most segments did in the 2008/2009 economy.

That's according to a report from iSuppli Corp, which estimated shipments will rise to record levels in 2010.

Shipments of silicon for semiconductor manufacturing in 2010 will grow by 23.6% year-over-year, reaching 8.9 billion total square inches, up from 7.2 billion square inches in 2009, iSuppli forecast. Growth is expected to continue and iSuppli projected that by 2014 12.4 billion total square inches of silicon will be shipped.

read more here....