Thursday, 13 September 2012

Power & Performance: GSS Sees SOI Advantages for FinFETS

Posted by Adele HARS on August 31, 2012, at Advanced Substrate News

Power & Performance: GSS Sees SOI Advantages for FinFETS

Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere.  But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.

The GSS IEDM ’11 Paper

GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks.  The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.
At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones.  Then they also need to provide reliable models to designers who will use them before committing chips to silicon.  One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs.  This covered  “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”.  Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project.  It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:
  • A key objective of the MODERN (for Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”.  Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
  • The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.


Sunday, 2 September 2012

CMRF Workshop (at BCTM)

CMRF Workshop (at BCTM)
Wednesday October 3, 2012, in Portland, Oregon, USA

Session Chair: Colin McAndrew
As with previous years the Workshop on Compact Modeling for RF/Microwave Applications (CMRF) is being held in conjunction with BCTM. The workshop has an interactive dynamic, and this year includes a Forum of experts who will assess the present major needs in modeling.

1:00–1:30 PM – Advanced SiGe HBT Modeling with HICUM Level 0 (v1.3) for RF and mmW Applications
D. Celi and N. Derrier
This presentation deals with advanced bipolar modeling using the latest revision of HICUM/L0 (1.3). Following an overview of test structures and measurement setup used for bipolar transistors, the new HICUM/L0 formulations are described. Subsequently a workflow for parameter extraction is detailed that is suitable for advanced SiGe heterojunction bipolar transistors for mmW applications. As a last point the possibilities and limitations of the model and the parameter extraction are discussed.

1:30–2:00 PM – Dynamic Ageing Modeling for Reliability Simulation
B. Ardouin
Semiconductor device behavior is not static but changes over time, and the amount of change depends on details of the voltages and currents a device experiences. This presentation will review recent development of a dynamic ageing model for HiCuM 2.3 and provides details of Verilog-A implementation and pragmatic modeling issues related to self-consistent integration of transistor degradation in accelerated time based on realistic transient circuit operation.

2:00–2:30 PM – End-to-End Modeling for Handset Power Amplifiers – It’s Not Just Two Transistors!
P. Zampardi, Y. Yang, K. Kwok, B. Li, A. Metzger, C. Cismaru, H. Shao, W. Sun, and M. Fredriksson
The short design cycle for handset power amplifiers relies on accurate models for ALL components used in the design, not just the “two HBTs” used for the power transistors. As the complexity of these amplifiers (usually used in front-end modules) has increased, so has the required accuracy for simulating the package, control circuitry, and the RF chain itself. This presentation will show some of the challenges and solutions developed to address the development of high-yield commercial power amplifiers and the design flow for their realization.

2:50–3:20 PM – Practical Modeling: When Less is More
A. DiVergilio
The primary goal of compact modeling is to allow designs to be carried out quickly and efficiently. Therefore, model accuracy is not the only metric of model effectiveness. No matter what the circuit, significant portions of the design cycle can benefit more from rapid iteration than from absolute accuracy. Overly-complicated models slow down simulation and, at worst, prevent convergence all-together, especially for large designs. This presentation discusses trade-offs that can be made between speed and accuracy, emphasizing the flexibility that can be achieved through high-level modeling languages, such as Verilog-A, when applied to device-level model development.

3:20–4:20 PM – Forum: “Grand Challenges in Modeling”
Queen Marie Ballroom
Models are by definition imperfect, but what are the biggest opportunities for improvement that will have the biggest bang-for-the-buck in design? This forum will attempt to answer that question, and formulate a prioritized list of items that will be published on the BCTM web site.


  • Bertrand Ardouin (XMOD technologies)
  • Adam DiVergilio (Tektronix)
  • Mikhail Shirokov (Triquint Semiconductor)
  • Peter Zampardi (Skyworks Solutions)
  • Colin McAndrew (Moderator; Freescale)