Tuesday, 31 August 2010

HP and Hynix - Bringing the memristor to market in next-generation memory

Today, HP announced a joint development agreement with Hynix Semiconductor Inc., to develop a new kind of computer memory – one that will employ memristor technology pioneered by researchers at HP Labs.

Monday, 30 August 2010

LDMOS - Technology and Applications

Speaker: Shekar Mallikarjunaswamy, Alpha Omega Semiconductor
Date: Sept 14th, 2010
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara , CA 95051 .

Abstract: A key device that is used in most high voltage (20 to 120V) power integrated circuits for power management applications is the Lateral Diffused MOS (LDMOS) transistor. Recent interest in ‘green” products have further increased the demand for integrated HV LDMOS devices in CMOS and BCD technologies to build higher efficiency dc-dc converters for consumer and LED markets. This presentation will journey through the structural innovations from “planar” to “trench” and to state-of-the-art “RESURF” LDMOS devices in both junction and dielectric isolation technologies for the past two decades. The physics of operation, figure of merits used for device comparison, layout techniques including integration of LDMOS into modern CMOS/BCD technologies will be discussed. Device and process simulations to optimize device parameters including SPICE macro circuits to model “quasi-saturation” and “Cgd” capacitance will be described. Methods to improve hot carrier reliability and ESD robustness of LDMOS devices will be highlighted. Finally, LDMOS circuit topologies and their applications in consumer, computer and telecommunication products will be presented to let the audience comprehend and appreciate the significance of LDMOS devices to modern power management products.

Web link: http://www.ewh.ieee.org/r6/scv/eds/

Wednesday, 18 August 2010

Modeling Memristor with SPICE

In 1971, Professor Chua proposed [1] that by necessity of symmetry reasons, besides the resistor, the capacitor, and the inductor; a fourth circuit element has to exist. In 2008, members of an HP Lab published [2] that they successfully realized a nano-scale electronic component. Spice macromodel [3-6] could be a powerful tool for electrical engineers to design and experiment new circuits with memristors.

REFERENCES
[1] L. Chua, “Memristor: The missing circuit element,” IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507–519, Sep. 1971.
[2] D. B. Strukov, G. S. Snider, D. R. Stewart, and S. R. Williams, “The missing memristor found,” Nature, vol. 453, no. 7191, pp. 80–83, May 2008.
[3] H.H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," DATE, 2010.
[4] Á. Rak and G. Cserey, "Macromodeling of the Memristor in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, 2010, pp. 632-636.
[5] D. Batas and H. Fiedler, "A Memristor Spice Implementation and a New Approach for Magnetic Flux Controlled Memristor Modeling," IEEE Transactions on Nanotechnology, 2010, pp. 1-1.
[6] "Modeling the HP memristor with SPICE," http://www.neurdon.com/2010/07/23/modeling-the-hp-memristor-with-spice/, 2010.

Tuesday, 17 August 2010

How To Make a P-N-P-N Semiconductor Device

50 years ago this year, in its 'Patent Pointers' section, the Electronics Weekly edition of September 14th 1980 carried the following snippet.

'An ingenious way of making a P-N-P-N or an N-P-N-P semiconductor device which avoids the difficulty of the heat treatment of the second junction adversely affecting the first formed junction is described in Patent No. 844970, filed by British Thomson-Houston Co.'

The note continues:
'What is done is to form a first P-N junction by alloying semiconductor germanium of N type with semiconductor silicon of P type, the second junction being subsequently made by fusing indium to the germanium.'

The note ends:
'The second junction is made at a lower temperature than the first so that the first junction is unharmed.'

Posted by David Manners on August 17, 2010; TrackBack URL for this entry:
http://www.electronicsweekly.com/cgi-bin/mt/mt-tb.cgi/162252

Friday, 13 August 2010

DATE 2011 - Final Call for Papers

DATE 2011 - Conference and Exhibition
March 14-18, 2011; Grenoble, France

Submission Deadlines:
  • Sept. 5, 2010: Papers, Special Sessions, Tutorials, Workshops
  • Oct. 10, 2010: Exhibition Theatre
  • Nov. 12, 2010: PhD Forum
  • Jan. 14, 2011: University Booth
More Information:
Download/View the CfP as PDF
Complete DATE 2011 information is available

Tuesday, 10 August 2010

Postdoctoral Marie Curie Fellowship on Compact Modeling

The European (7th Framework Programme) Call for Postdoctoral Individual Marie Curie Fellowships is open until August 17 2010.

I am looking for one or two candidates to work in my research group at the Universitat Rovira i Virgili (Tarragona, Spain) in the field of compact modeling of advanced semiconductor devices. Therefore, I would like to receive CVs from potential applicants. Once I have selected the candidates, we will make the application.The candidates must have a Ph D in Electrical Engineering, Electronic Engineering, Physics or Telecommunication Engineering.

There are two open Calls: the one forIntra-European Fellowships and the one for International Incoming Fellowships. Therefore, candidates from European countries can apply for an Intra European Fellowship and candidates from outside Europe can apply for an International Incoming Fellowship.These felowships can be for one or two years. Salaries are extremely good and the prestige of having this type of fellowship is very high. For this reason, there is a tough competition to get these fellowships.I am looking for candidates for these Marie Curie Grants, both from Europe and outside Europe. Candidates must have a good CV (preferably with more than 4 publications in international journals, in order to have chances).

In order to fit the Marie Curie requirements, their age should be below 35.

If successful, the postdoctoral researchers will work on the characterization of compact modeling of any of the advanced semiconductor devices targeted by our research European projects: nanoscale MOSFETs, SOI and Multi-Gate MOSFETs, strained-Si/SiGe MOSFETs, Schottky-Barrier MOSFETs, nanowire FETs, III-V HEMTs and organic TFTs.The specific device/s in which the postdoctoral researcher will work will depend on his/her preference and background.

Candidates must send me by e-mail (to benjamin.iniguez@gmail.com) a CV or resume by AUGUST 14. Successful applicants will be informed by August 15, and then we will start to make the application. The successful candidates will be informed on the steps to do.

Tarragona is a small city (110000 inhabitants) on the Mediterranean coast, about 100 Km south from Barcelona, and very well connected to Barcelona and the main Spanish cities by rail and highway. Tarragona is a very old city, very important during the Roman Empire, and with a lot of historical landmarks.The quality of life in Tarragona is excellent. Mediterranean and mild climate the whole year. Wonderful beaches around the city (even at the city). Mountains close to the city (even the Pyrenees are not far). Besides, the city is very quiet, but with an intense nightlife.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling (in which a total of 15 European universities and companies participate). We also participate on two other European projects (one about nanoscale MOSFETs and another one about organic Thin Film Transistors). I am looking forward to receiving excellent applications!
Benjamin Iñiguez
Department of Electronic EngineeringTarragona,
SPAIN
Universitat Rovira i Virgili (URV)
E-mail: benjamin.iniguez@gmail.com

Sunday, 8 August 2010

[mos-ak] Final Program MOS-AK/GSA Workshop in Seville

Please visit the MOS-AK/GSA/ESSDERC/ESSCIRC Seville web site with the
final workshop program:
http://www.mos-ak.org/seville and
http://www.mos-ak.org/seville/posters.php

* Venue and Recommended Hotels:
Sept.17, 2010 Barceló Renacimiento Hotel Seville
http://www.barcelorenacimiento.com/

* Free On-line Registration Form:
http://www.essderc2010.org/registration.html
or send an email directly to <seville@mos-ak.org>

Your might also note that, it will have a series of important compact
modeling (CM) events is Spain:

  • Sept. 9-10: CMC Q3 Meeting with the COMON project presentation
  • Sept. 13: ESSDERC CM tutorial
  • Sept. 16: ESSDERC CM session with the regular conference papers
  • Sept. 16: COMON CM Project Meeting
  • Sept. 17: MOS-AK/GSA CM Workshop

--
For more options, visit www.mos-ak.org or its email group at:

Sunday, 1 August 2010

Open Ph D scholarship in semiconductor device modeling

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.


The duration of the grant will be for four years. The monthly salary will be about 1000 Euro/month. The position will start in January 2011.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs or III-V devices. It will be related to several European projects in which the hosting group participates, in particular the COmpact MOdelling Netwok (COMON), that is led by the hosting group (the so-called NEPHOS group)

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.


Required documents for applicants


Applicants are required to send to the address specified below the following documents (in English or Spanish):

1) a full Curriculum Vitae (as complete as possible) with passport number

2) Copy of their diploma

3) copy of their passport

4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates are requested to send their documents by e-mail to:

Prof. Benjamin Iñiguez
Department of Electronic, Electrical and Automatic Control Engineering

Universitat Rovira i Virgili (URV)

Avinguda Països Catalans, 26
43007
Tarragona (Spain)
Email: benjamin.iniguez@gmail.com
Tel: +34977558521 Fax:+34977559610


Deadline: August 21 2011

You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat and sauron.etse.urv.es