Oct 4, 2018

[mos-ak] [2nd Announcement and C4P] 11th International MOS-AK Workshop, Silicon Valley, December 5, 2018

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
11th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 5, 2018

Together with Silvaco, lead sponsor and local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 11th International MOS-AK Workshop which will be organized at Silvaco HQ on Dev. 5, 2018 (co-located with the IEDM and CMC Meetings)

Planned 11th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue
Silvaco
2811 Mission College Blvd., 6th Floor
Santa Clara, California 95054

Online Workshop Registration is open 
(any related enquiries can be sent to registration@mos-ak.org)

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Sept. 2018
  • 2nd Announcement - Nov. 2018
  • Final Workshop Program - Oct. 2018
  • MOS-AK Workshop: Dec. 5, 2018
Online Abstract Submission is open 
(any related enquiries can be sent to abstract@mos-ak.org)

Postworkshop IJHSES Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG041018

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Oct 1, 2018

[mos-ak] [2nd Announcement and Call for Papers] 2nd MOS-AK/India Conference, IIT Hyderabad, Feb. 25-27, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
2nd MOS-AK/India Conference
IIT Hyderabad
Feb. 25-27, 2019 

Together with the MOS-AK/India Steering Committee and executive local organizers at the IIT Hyderabad as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 2nd MOS-AK/India Conference at IIT Hyderabad between Feb. 25-27, 2019 

Venue
Indian Institute of Technology (IIT) Hyderabad
Hyderabad, Kandi
Telangana State, India

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

Compact Modeling Track  
Circuits and Systems Track  
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • FOSS TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT and SOI-based memory cells
  • Organic, Bio/Med devices/technology modeling
  • Microwave, RF device modeling, HV/Power device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D reliability/ageing, DFY, DFT 
  • Foundry/Fabless Interface Strategies
  • Analog Circuits
  • Biomedical and Life-Science Circuits, Systems and Applications
  • Circuits and Systems for Communication
  • Emerging Technologies for Circuits and Systems
  • HP/HV IC Designs
  • Memory Circuits and Systems
  • Mixed Signal Circuits
  • RF/mm-Wave IC Design and Technology
  • Sensory Systems System-on-Chip and CAD
  • Testing Technology
  • VLSI Systems & Applications
  • And any other IC design related topic

Online Abstract Submission (any related enquiries can be sent to secretary.mosak.india@gmail.com)

Original unpublished works in topics related to the following areas (but not limited to) can be submitted for publication. The proceedings of the conference will be submitted to IEEE Explore. Best Paper Award: Gold leaf, Silver leaf and Bronze leaf certificates will be given to best papers.

Highest Ranked papers from regular submission will be invited to extend their paper in the form of a book chapter. All these submission will be published in the form of a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoters of MOS-AK/India 2019 Conference. 
Author Instruction and Registration Details available as a pdf document

Important Dates:
Call for Papers - 1 Sept. 2018
2nd Announcement -  1 Oct. 2018
Paper and Tutorial Submission Deadline - 1 Nov. 2018
Notification of Acceptance - 15 Dec. 2018
Registration and Camera Ready Paper Submission - 10 Jan. 2019
Final Conference Program - 15 Jan. 2019
MOS-AK/India Conference - February 25-27, 2019
Online registration (to be open in Jan. 2019; any related enquiries can be sent secretary.mosak.india@gmail.com)

Extended MOS-AK Committee


WG010118
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Sep 30, 2018

Sep 28, 2018

New Charge Pumping Current #Model Assuming Exponential Tails in the Trap Energy Distribution. This modified expression leads to a different method of extracting the trap emission time constant https://t.co/LUtOI11Och


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September 28, 2018 at 12:20PM
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Sep 27, 2018

System76 To Release A "New #opensource #Computer" https://t.co/CglryyCNZU https://t.co/SN8OYHydYb


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September 27, 2018 at 05:14PM
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[paper] Importance of complete characterization setup on onwafer TRL calibration in sub-THz range

Chandan Yadav, Marina Deng, Magali De Matos, Sebastien Fregonese
and  Thomas Zimmer
IMS Laboratory, University of Bordeaux
351 cours de la LibĂ©ration – 33405 Talence cedex, France

Abstract: In this paper, we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test-structures calibrated with on-wafer TRL. These results are compared against 3D EM simulation of the intrinsic test-structures. To analyze difference between the measured and intrinsic EM simulation results, onwafer TRL calibration performed on EM simulation results of a dedicated test-structure is also presented. 

FIG: 3D view of the Open-M1 where metal-1 (M1) does not have connection with ground as shown in the enlarged view.



Sep 26, 2018

#Modeling of Electron Devices Based on 2-D Materials. Shortly analyze the main open challenges of modeling 2-D-based electron devices. https://t.co/GkhpFYFS3H


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September 26, 2018 at 02:48PM
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