Jul 24, 2018

Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1 https://t.co/T4cI4ySoH1


from Twitter https://twitter.com/wladek60

July 24, 2018 at 09:18PM
via IFTTT

Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1


from Twitter https://twitter.com/wladek60

July 24, 2018 at 09:18PM
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Characterization and #Modeling of Temperature Effects in #3D #NAND Flash Arrays—Part II: Random Telegraph #Noise https://t.co/gQUJCnoP3O


from Twitter https://twitter.com/wladek60

July 24, 2018 at 05:13PM
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A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8 https://t.co/68fIGLy7M8


from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
via IFTTT

A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8


from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
via IFTTT

Jul 18, 2018

[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018

MOS-AK Workshop at ESSDERC/ESSCIRC
Dresden, Sept. 3, 2018

Subsequent MOS-AK modeling workshop organized at ESSDERC/ESSCIRC in Dresden on Sept. 3, 2018, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:

Venue:
Technische Universität Dresden
room CHE/0184/U
Dresden (D)

Agenda:
  • MOS-AK Workshop: Sept. 3, 2018
  • ESSDERC Track4 "Compact modeling of devices and circuit" Sept. 5-6, 2018
    • Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
      Chair: Wladek Grabinski, Thierry Poiroux
    • Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
      Chair: Daniel Tomaszewski, Benjamin Iniguez
(any related inquiries can be sent to registration@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems


WG180718

 

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