Post Doctoral Researcher / Research Engineer Position in Compact Modeling

The BSIM Group of Electrical Engineering Department at the University of California Berkeley is seeking to hire a bright candidate interested in compact model development/maintenance to join as a post doctoral researcher or research engineer. We are looking for a candidate with PhD (for post doctoral researcher) or Masters (for Research Engineer) degree in EE/Physics preferably for long term (4–5 years). The responsibilities include but not limited to

• Research and development of new BSIM compact models
• Maintenance and support of BSIM MOSFET compact models (BSIM4, BSIMSOI and BSIM-MG)
• Interface with industry to understand requirements and issues with BSIM models and rectify them
• C & Verilog-A coding and testing/debugging of models

Required skills

• Excellent semiconductor device physics and process technology knowledge
• Experience in computer programming (C and Verilog-A)
• Knowledge of basic analog and digital circuit operation

BSIM Group encourages its members to represent it actively at conferences, workshops, and meetings. Interested applicants should submit their CV to bsimgroup@gmail.com

For more information, please visit:
BSIM Group and Device Group

Nature Materials | Letter

Arrays of indefinitely long uniform nanowires and nanotubes

• Mecit Yaman,
• Tural Khudiyev,
• Erol Ozgur,
• Mehmet Kanik,
• Ozan Aktas,
• Ekin O. Ozgur,
• Hakan Deniz,
• Enes Korkut
• & Mehmet Bayindir

• Affiliations
• Contributions
• Corresponding author

Nature Materials 10, 494–501 (2011)

doi:10.1038/nmat3038

http://www.nature.com/nmat/journal/v10/n7/full/nmat3038.html


It's frankly nice.... see one of their pictures (hope they don't get too upset!):

SISPAD 2011 Companion Workshops

September 7, 2011; Hotel Hankyu Expo Park, Osaka, Japan

• Compact Modeling
• Organizer: Sadayuki Yoshitomi, Toshiba Corporation
• Power Devices
• Organizer: Ichiro Omura, Kyusyu Institute of Technology

[link]

SuVolta creates new transistor option for 20 nm

SuVolta creates new transistor option for 20 nm: "SuVolta, a startup process IP company with deep roots indevice design and m..."

Job offers at RF Micro Devices (RFMD)

I've seen that there are three job offers for Compact Modeling engineers at RFMD:

Tracking Code           Job Title             Location            Date Posted

12134

Senior Modeling Engineer

Greensboro, NC, US

6/7/2011

12117

Sr. TCAD Modeling Engineer

Greensboro, NC, US

5/26/2011

12116

Sr. Modeling Engineer

Greensboro, NC, US

5/24/2011

Note that this is only a re-diffusion of some information we've got, and that we're not related to them in any way!

Get your own version of Myfab LIMS

Myfab is the Swedish national research infrastructrue for micro and nano fabrication. Use the best cleanroom facilities in Sweden through our laboratory network and bring new scope and opportunity to your research and technical development. [read more]

IMEC benchmarks FinFET superiority

IMEC benchmarks FinFET superiority:

By Peter Clarke, EE Times -- EDN, June 16, 2011

LONDON - The IMEC research institute has compared one planar and two FinFET technologies to see how they perform against scaling and process variability.

The benchmark circuits were six-transistor SRAM cells and SRAM arrays and IMEC has concluded that the FinFET outperforms planar CMOS in variability-aware and technology-aware comparison of SRAM product yield.

Both FinFET on bulk and FinFET on silicon-on-insulaor (SOIFF) technologies come out superior to the planar technology for medium- to large-sized SRAM arrays resulting in higher yields, IMEC said, although it did not disclose the process geometry at which the tests were done. It is likely to have been at around 28 to 22 nm.

As the dimensions of devices scale down, the variations in the electrical parameters of CMOS transistors steadily increase. This is due to random fluctuations in the density of the dopants in the channel, source, and drain. So, two closely placed transistors that are supposedly identical can show a widely different behavior. This makes the design of SRAM memory cells less predictable and controllable for every new technology node.

Because of this scaling 6T planar SRAMs below 22 nm remains challenging, IMEC said. FinFET devices show a lower leakage and variability and it is possible to design more compact cells.

Both FinFET technologies come out as superior to planar for SRAM arrays of greater than 128 kbytes. They are less sensitive to mismatches, thus allowing a more aggressive scaling of the power supply and a lower VCC than planar arrays. For undoped silicon-on-insulator FinFETs (SOIFF), the power supply can be lowered by an additional 200-mV compared to planar. As a sample result: undoped SOIFF FinFET allow for a 95% yield at 0.7-V in 32-Mbit SRAM arrays, moving to Gbit arrays for higher voltages.