Jun 17, 2010

An interesting (educative?) post in EDN by Paul Rako :

Op-amp Spice macro-models article from Intersil

June 16, 2010
Former EDN analog editor Bill Schweber has published a good article from Tamara Schmitz and Jian Wong about developing Spice macromodels for voltage-feedback op-amps. Part 1 (pdf), and part 2 (pdf). All the youngsters like to use Spice for op-amp circuit design but I am more like Bob Pease and Jim Williams, you have to build the circuit to know what is going on. I will never forget being perfectly happy with a Spice run, until I built the circuit and realized that the quad op amp was running way too hot. I did not notice the power consumption of each of the amps was about ¼ W. That was a newbee mistake, sure, but even if Spice does not lie, it is the product of digital and software minds, so rather than flashing a big red sign that warns you that you are going to burn up the quad op amp, they just require you to define a power variable and display it and then print the result in the same tiny test and the blizzard of other information. Then software people smile and fold their arms and tell us everything is our fault, since the information was right there if only we asked for it.  The one thing about analog is that is has a sense of importance. That’s why steering wheels and shift levers are big and prominent and radio treble controls are tiny little buttons. If software people designed cars everything would be a tiny little icon and the crash warnings would be in 10-point text.
So anyway, Spice does not necessarily lie like Bob Pease says, but I guarantee you that if you give it poor models it will give you the wrong answer. This is the big hassle with op amp models. Some of them, like the old National Semi Comlinear models (pdf) published by Mike Steffes before he left for Burr Brown and now Intersil were essentially transistor-level models. An IC designer could infer the design of the part from them. Mike told me that he knew that, but it was just so important to give an accurate model that he felt he had to release those great models. If someone wanted to copy the circuits, well, they had a lot more work to do-anyone can de-cap an op amp and reverse engineer it in a day. That still does not give you the process or the testing regime or the design secrets and tricks.
That is why this Intersil article is so important. Anything that helps you make good models is important in a world where kid engineers trust a computer rather than a breadboard. The article give some history of op amp models and that will tip you off as to what you can expect from a simulation. If the model you use does not model for 1/f noise, and most vendor models do not, you cannot get a meaningful simulation of low-frequency noise performance of the circuit. If the model does include flat-band noise and you are designing and ac-coupled video circuit, well that is fine for your needs. I have yet to see a Spice op-amp model that accurately tells you what happens if you bang the output into the rails and saturate the transistors. I will ask Mike Steffes if his old Comlinear models would do that, and leave a comment.

Jun 15, 2010

Modeling The Bipolar Transistor (Book)

Modeling The Bipolar Transistor (*)
By Ian Getreu
(2009; Paperback, 286 pages)

The book describes the bipolar transistor model and parameter measurement techniques for the SPICE circuit simulator. Originally published by Tektronix in 1974, this is a slightly modified revision republished in 2009 by the original author.

Read the review by Colin McAndrew

(*) There is a $4.00 discount if people order it by June 30 - use the coupon code: SUMMERREAD305.

Jun 11, 2010

IEEE Awards 2010


Takayasu Sakurai, has got the 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, for pioneering contributions to the design and modeling of high-speed and low-power CMOS logic circuits.



Note that this is not compact modeling, but his alpha power law model has had a big impact!


Gennady Gildenblat has got promoted to IEEE Fellow for his "contributions to modeling of metal-oxide semiconductor field effect transistors".

Yasuhisa Omura has got promoted to IEEE Fellow for the contributions made to the SOI technology, analysis and modelling.

Thomas Piotr Skotnicki also got the promotion to IEEE Fellow for contributing to the development of MOS models.



Congratulations to all of them!

Jun 8, 2010

Physicists from Mainz University develop a quantum interface between light and atoms



Ultra-thin glass fiber enables the controlled coupling of light and matter / publication in Physical Review Letters:

E. Vetsch, D. Reitz, G. Sagué, R. Schmidt, S. T. Dawkins, and A. Rauschenbeutel
Optical interface created by laser-cooled atoms trapped in the evanescent field surround-ing an optical nanofiber
Physical Review Letters, May 21, 2010
DOI: 10.1103/PhysRevLett.104.203603

Jun 7, 2010

2010 IEDM CALL FOR PAPERS

Submission Deadline is June 25, 2010!

The IEEE International Electron Devices Meeting is the Annual Technical Meeting of the Electron Devices Society.  This year it will be held at the Hilton San Francisco Union Square, San Francisco, CA USA December 6-8, 2010.

Increased participation in the areas of energy harvesting, power devices, biomedical devices and circuit-technology interaction is desired.

Information about IEDM can be found at: http://www.ieee-iedm.org

Social Networking: 
Twitter: http://twitter.com/ieee_iedm
 
Facebook:
http://www.facebook.com/search/?q=IEDM&init=quick#/pages/IEDM/131119756449?ref=search&sid=6112806.762392748..1



MEETING HIGHLIGHTS 
 * Three plenary presentations by prominent experts. 
 * Invited papers on all aspects of advanced devices and technologies. 
 * An Emerging Technology session. 
 * Panel discussion.
 * Presentation of IEEE/EDS awards. 
 * IEDM Luncheon presentation will be held on Tuesday, December 7.
 * Two short courses will be held on Sunday December 5.

Abstract Submission
 * Web-based submission of abstracts (http://www.ieee-iedm.org)
 * Deadline for submissions is June 25, 2010 

For further information on submissions, go to http://www.ieee-iedm.org and click on call for papers.  Download the pdf of the call for papers with more detailed information.

Questions/Comments, contact the IEDM Conference office at:
phyllism@widerkehr.com or 301-527-0900 ext. 2

Jun 3, 2010

Training Course on Compact Modeling: Final Programme

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

I want to remark that ON JUNE 30 AND JULY 1 THERE ARE NO SOCCER WORLD CUP MATCHES.

So, participants do not have to worry to miss soccer matches during the duration of the Training Course!


The final programme, with the timetable, is already available:


Day 1: June 30, 2010 (Wednesday)
8:15
Training Courses Opening
Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
8:30
Statistical variability and corresponding compact model strategies
Asen Asenov (University of Glasgow)
9:45
Electrical characterization of SOI and Multi-Gate MOSFETs
Sorin Cristoloveanu (MINATEC and LETI, France)
11:00
Coffee Break
11:30
Transport modeling
Tibor Grasser (TU-Wien, Austria)
12:45
Analytical 2D and 3D electrostatic modeling
Tor A Fjeldly (UniK, Norway)
14:15
Lunch
15:15
Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs
Kiyoo Itoh (Hitachi, Japan)
16:30
GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization
Wladek Grabinski
20:30
Gala Dinner






Day 2: July 1, 2010 (Thursday)
8:30
Analytical small-signal modeling
Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
9:45
DC Parameter Extraction
Antonio Cerdeira (Cinvestav, Mexico)
11:00
Coffee Break
11:30
Compact, High Frequency Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET
Ilcho Angelov (Chalmers University, Sweden)
12:45
Noise modeling
Jamal Deen (McMaster University, Canada)
14:15
Lunch
15:15
Electro-thermal and reliability modeling
Renaud Gillon (On Semiconductor, Belgium)
16:30
Leakage power modeling for the reduction of power consumption in CMOS ICs
Massimo Poncino (Politecnico di Torino, Italia)
17:45
Training Courses Closing

And nice weather is usual in Tarragona at the end of June/beginning of July. Participants who spend a few more days in Tarragona can enjoy the nice beaches around, or doing sightseeing in the Tarragona area, Barcelona (only 100 Km far from Tarragona) and other places in Catalonia.

Tarragona is well connected to Barcelona by rail and highway. There are direct buses from Barcelona Airport. Besides, there are direct flights to Reus Airport (less than 15 Km far from Tarragona) from many European cities by Ryanair.

STM confirms 20nm by end of 2012

The chief technology officer at STMicroelectronics, Jean-Marc Chery, today confirmed at the Field Trip conference in London that its first 20nm process will be going into production at its French fab by Q4 2012. [more]

Intel's timbers could be shivered. In Q1 2010 alone ST had revenue of $2,323 million USD and it was the #1 EMEA semiconductor company in 2009.