Jun 7, 2010

2010 IEDM CALL FOR PAPERS

Submission Deadline is June 25, 2010!

The IEEE International Electron Devices Meeting is the Annual Technical Meeting of the Electron Devices Society.  This year it will be held at the Hilton San Francisco Union Square, San Francisco, CA USA December 6-8, 2010.

Increased participation in the areas of energy harvesting, power devices, biomedical devices and circuit-technology interaction is desired.

Information about IEDM can be found at: http://www.ieee-iedm.org

Social Networking: 
Twitter: http://twitter.com/ieee_iedm
 
Facebook:
http://www.facebook.com/search/?q=IEDM&init=quick#/pages/IEDM/131119756449?ref=search&sid=6112806.762392748..1



MEETING HIGHLIGHTS 
 * Three plenary presentations by prominent experts. 
 * Invited papers on all aspects of advanced devices and technologies. 
 * An Emerging Technology session. 
 * Panel discussion.
 * Presentation of IEEE/EDS awards. 
 * IEDM Luncheon presentation will be held on Tuesday, December 7.
 * Two short courses will be held on Sunday December 5.

Abstract Submission
 * Web-based submission of abstracts (http://www.ieee-iedm.org)
 * Deadline for submissions is June 25, 2010 

For further information on submissions, go to http://www.ieee-iedm.org and click on call for papers.  Download the pdf of the call for papers with more detailed information.

Questions/Comments, contact the IEDM Conference office at:
phyllism@widerkehr.com or 301-527-0900 ext. 2

Jun 3, 2010

Training Course on Compact Modeling: Final Programme

The first edition of the Training Courses on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 30-July 1, in coordination with two other events partially or totally related to compact modeling: the 8th Graduate Student Meeting on Electronic Engineering (June 28-29) and the 3rd International Workshop on Compact Thin Film Transistor Modeling (July 2).

The Training Course will consist on 12 lectures addressing relevant topics in the compact modeling of advanced electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Courses on Compact Modeling are sponsored by the European Union FP7 “COMON” IAPP Project, the European Union FP7 NANOSIL Network of Excellence and the Universitat Rovira i Virgili in collaboration with the IEEE EDS Compact Modeling Technical Committee.


REGISTRATION IS OPEN

It is cheap and includes two lunches and one gala dinner. The advanced registration fee will be 100 Euro for students and 130 Euro for non-students. After June 13, the registration fee is 150 Euro for students and 180 Euro for non-students. Members of the teams participating in the COMON project are exempted from paying the fee, and members of teams participating in NANOSIL pay a reduced fee.

I want to remark that ON JUNE 30 AND JULY 1 THERE ARE NO SOCCER WORLD CUP MATCHES.

So, participants do not have to worry to miss soccer matches during the duration of the Training Course!


The final programme, with the timetable, is already available:


Day 1: June 30, 2010 (Wednesday)
8:15
Training Courses Opening
Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
8:30
Statistical variability and corresponding compact model strategies
Asen Asenov (University of Glasgow)
9:45
Electrical characterization of SOI and Multi-Gate MOSFETs
Sorin Cristoloveanu (MINATEC and LETI, France)
11:00
Coffee Break
11:30
Transport modeling
Tibor Grasser (TU-Wien, Austria)
12:45
Analytical 2D and 3D electrostatic modeling
Tor A Fjeldly (UniK, Norway)
14:15
Lunch
15:15
Variability-conscious Circuit Designs for Low-voltage Nano-scale CMOS LSIs
Kiyoo Itoh (Hitachi, Japan)
16:30
GNU/Open Source CAD Tools for Verilog-A Compact Model Standardization
Wladek Grabinski
20:30
Gala Dinner






Day 2: July 1, 2010 (Thursday)
8:30
Analytical small-signal modeling
Benjamin Iniguez (Universitat Rovira i Virgili, Spain)
9:45
DC Parameter Extraction
Antonio Cerdeira (Cinvestav, Mexico)
11:00
Coffee Break
11:30
Compact, High Frequency Equivalent Circuit Models for GaN, SiC, GaAs and CMOS FET
Ilcho Angelov (Chalmers University, Sweden)
12:45
Noise modeling
Jamal Deen (McMaster University, Canada)
14:15
Lunch
15:15
Electro-thermal and reliability modeling
Renaud Gillon (On Semiconductor, Belgium)
16:30
Leakage power modeling for the reduction of power consumption in CMOS ICs
Massimo Poncino (Politecnico di Torino, Italia)
17:45
Training Courses Closing

And nice weather is usual in Tarragona at the end of June/beginning of July. Participants who spend a few more days in Tarragona can enjoy the nice beaches around, or doing sightseeing in the Tarragona area, Barcelona (only 100 Km far from Tarragona) and other places in Catalonia.

Tarragona is well connected to Barcelona by rail and highway. There are direct buses from Barcelona Airport. Besides, there are direct flights to Reus Airport (less than 15 Km far from Tarragona) from many European cities by Ryanair.

STM confirms 20nm by end of 2012

The chief technology officer at STMicroelectronics, Jean-Marc Chery, today confirmed at the Field Trip conference in London that its first 20nm process will be going into production at its French fab by Q4 2012. [more]

Intel's timbers could be shivered. In Q1 2010 alone ST had revenue of $2,323 million USD and it was the #1 EMEA semiconductor company in 2009.

Jun 2, 2010

Toshiba Invention Brings Quantum Computing Closer

Quantum computers are likely to be used initially to solve problems that are otherwise virtually intractable, such as modeling new molecules in pharmaceuticals. The Toshiba team, working with the University of Cambridge's Cavendish Laboratory, described their invention in a paper in the journal Nature.

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Jun 1, 2010

Fastest Integrated Circuit Doubles the Previous Record, Getting Close to One Terahertz


The 670 GHz compact circuit layout (right), alongside a detail of Northrop Grumman's 30-nanometer Indium Phosphide T-gate (left). Northrop Grumman [more]