Apr 5, 2012

Job Offer in SanDisk (april, 2012)

Remember: we are only re-posting this information, and we're not related to the offer in any other form.

Job Description

In this position, the individual will work in the NAND Flash team to generate IBIS models for the NAND IO’s to be finally used by the internal System team & external customers. In this highly visible role you will perform the following duties:
  • Develop IBIS models for the Legacy and DDR IO’s.
  • Develop HSPICE models for Legacy and DDR IO’s.
  • Interact with the US & the India team.
  • Over a period of time develop a team for IBIS models.
  • Develop an automated methodology on developing the models

Desired Skills & Experience

This position requires a Bachelor or Master Degree in Electrical/ (Micro) Electronics / VLSI Engineering or equivalent. 2 to 8 years of experience in IBIS models development for the complex Input/Output Buffers. Understanding about the functionality of complex IO’s.Should have deep understanding about HSPICE simulators & IBIS tools e.g Magma Silicon Smart. Excellent Team player.

Company Description

SanDisk Corporation is the global leader in flash memory cards - from research, manufacturing and product design to consumer branding and retail distribution. SanDisk's product portfolio includes flash memory cards for mobile phones, digital cameras and camcorders; digital audio/video players; USB flash drives for consumers and the enterprise; embedded memory for mobile devices; and solid state drives for computers. SanDisk is a Silicon Valley-based S&P 500 company, with more than half its sales outside the United States.

Additional Information

Posted:
April 4, 2012
Type:
Full-time
Experience:
Mid-Senior level
Functions:
Engineering 
Industries:
Semiconductors 
Job ID:
2809898

Mar 30, 2012

[mos-ak] C4P MOS-AK/GSA Dresden Workshop (April 26-27, 2012)

Together with the Fraunhofer IIS, local organizer and Extended MOS-AK/GSA TPC Committee, we have pleasure to invite to the MOS-AK/GSA Dresden Workshop at Fraunhofer IIS, Zeunerstraße 38, D-01069 Dresden on April 26-27, 2012; with XFAB visit and networking event.

On-Line free registration is open:
http://mos-ak.org/dresden/registration.php

MOS-AK/GSA Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. Topics to be covered include the following:
 * Advances in semiconductor technologies and processing
 * Compact Modeling (CM) of the electron devices
 * Verilog-A language for CM standardization
 * New CM techniques and extraction software
 * CM of passive, active, sensors and actuators
 * Emerging Devices, CMOS and SOI-based memory cells
 * Microwave, RF device modeling, high voltage device modeling
 * Nanoscale CMOS devices and circuits
 * Technology R&D, DFY, DFT and IC Designs
 * Foundry/Fabless Interface Strategies

Speakers tentative list (in alphabetic order) includes:
 * Klaus Gaertner, WIAS Berlin
 * Thomas Gneiting, Admos
 * Joachim Haase, Fraunhofer, IIS
 * Benjamin Iniguez, URV Tarragona
 * Wolfgang Mathis, Uni Hannover
 * Paolo Nenzi, Uni Roma
 * Andrej Rumiantsev, Cascade
 * Franz Sischka, Agilent
 * Jiri Slezak, On-Semi
 * Daniel Tomaszewski, ITE Warsaw
 * Dietmar Warning, Atmel

Intending participants and authors should also note the following deadlines:
 * Call for Papers - Mar. 30, 2012
 * Final Workshop Program - April 10, 2012
 * MOS-AK/GSA Workshop - April 26-27, 2012

On-Line abstracts submission is open:
http://www.mos-ak.org/dresden/abstracts.php

Further details and updates: <http://www.mos-ak.org/dresden> 
Email contact: <dresden@mos-ak.org>
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Mar 28, 2012

Introducing the 2012 IEEE Fellows

The IEEE Fellows class for 2012 has been announced on 5 March 2012. The Institute salutes these 329 IEEE senior members from around the world who have been named IEEE Fellows for 2012. They join an elite group of more than 6000 IEEE Fellows, who have contributed to the advancement or application of engineering, science, and technology.

Mar 26, 2012

2nd Training Course on Compact Modeling

Building on the success of its first edition in 2012, the 2nd Training Course on Compact Modeling (TCCM) will be held in Tarragona (Catalonia, Spain) on June 28-29 2012. It will be organized by will be organized by the NEPHOS Group, of the Department of Electronic, Electrical and Automatic Control Engineering at the Universitat Rovira i Virgili (Tarragona).. The General Chairman is Prof. Benjamin Iñiguez.

The Training Course on Compact Modeling will consist of 12 of lectures addressing relevant topics in the compact modeling of advanced electron devices. These lectures will be conducted by top experts in the field. Most of the lectures will target compact modeling issues applicable to many electron devices. In particular, emphasis will be given on MOSFETs (bulk, SOI, Multi-Gate and High Voltage MOS structures) and HEMTs.

The Training Course on Compact Modeling is an event sponsored by the FP7 “COMON” (COmpact MOdelling Network) IAPP Project (which is coordinated by the Universitat Rovira i Virgili) in collaboration with the IEEE EDS Compact Modeling Technical Committee.

The preliminary programme is already available at:

http://compactmodelling.eu/tccm2_programme.php

Prof. Raphaël Clerc (INPG, Grenoble, France)
"Tunnel and quasi-ballistictransport modelling in nanoscale MOS devices"

Prof. David Jiménez - Universitat Autònoma de Barcelona (UAB, Barcelona, Spain)
"Analytical quantum modelling of ultimate MOS devices"

Dr. Romain Ritzenthaler (IMEC, Belgium)
"3D analytical modelling techniques for Tri-Gate MOS structures"

Prof. Antonio Cerdeira (CINVESTAV,Mexico)
"Design-oriented compact modelling for Multi-Gate MOS devices"

Dr. Colin C. McAndrew (Freescale Semiconductors, Phoenix, AZ, USA)
"Statistical modelling techniques"

Dr. Thomas Gneiting (AdMOS GmbH, Frickenhausen, Germany)
"Flicker noise measurements and characterization"

Prof. Frédéric Martinez (Université de Montpellier 2, France)
"Low frequency noisemodeling"

Dr. Franz Sischka (Agilent Technologies, Böblingen, Germany)
"S-parameter and nonlinear RF modelling"

Prof. Giovanni Ghione (Politecnico di Torino, Italy)
"Thermal modelling of RF and microwave devices"

Prof. Jamal Deen (McMaster University, Canada)
"High frequencynoise modeling"

Prof. Mike Brinson (Metropolitan University of London, UK)
"QucsStudio: A second generation Qucs software package for compact semiconductor devicemodel development based on interactive and compiled equation-defined modellingtechniques plus circuit simulation"



Registration will be cheap, in particular before June 16 :

http://compactmodelling.eu/tccm2_registration.php

will include lunches, coffee breaks and a Gala Dinner on June 28, in a nice restaurant with TV screens to watch the Semifinals match of the Soccer European Cup ...

Besides, on June 25-27 the same group at URV will organize 8th International Conference on Organic Electronics (ICOE 2012) also in Tarragona. Participants to this Training Course will have a reduced fee for ICOE 2012.

I encourage compact modeling researchers to attend TCCM!

Mar 25, 2012

SBMicro symposium 2012

27th SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES CHIP IN BRASÍLIA
August 30 - 02, 2012
Hotel San Marco, Brasilia, DF - Brazil

http://chipinbsb.cic.unb.br/sbmicro.html

Call for Papers: The SBMicro symposium is an international forum dedicated to fabrication and modeling of microsystems, integrated circuits and devices, held annually in Brazil. The goal of the symposium is to bring together researchers in the areas of processing, materials, characterization, modeling, simulation and TCAD of integrated circuits, microsensors, microactuators and MEMS. The SBMicro2012 will be located in Brasília, Brazil. This international conference offers a unique blend of microelectronics and serves as a major conference for the discussion of interdisciplinary research around the world through a variety of formats, such as oral presentations, poster sessions, exhibits, panel discussions, and tutorial sessions. The best papers presented at the symposium will be invited to resubmit an extended version that will be considered for publication at the JICS - Journal of Integrated Circuits and Systems and at the Journal of the Electrochemical Society.

SBMicro2012 will occur in the same venue as SBCCI2012 - 25th Symposium on Integrated Circuits and Systems Design.

Deadline and Paper Format
  • Paper Submission Deadline: March 31th, 2012
  • Notification of Acceptance : May 18th, 2012
  • Camera-Ready Deadline : June 01th, 2012
SBMicro2012 will receive camera-ready submissions in English for consideration by the Program Committee with a maximum of 10 pages. Submission paper format details for SBMicro2012 are available at the conference website http://www.sbmicro.org.br/sbmicro. Simultaneous submissions or submissions of previously published papers will not be considered. The Program Committee will only accept electronics submission in PDF format via the conference website.
Topics of interest include, but are not limited to:
  • Semiconductor and MEMS processing;
  • Sensors and actuators;
  • Optoelectronics and photovoltaic;
  • Plasma technology and diagnostics;
  • Nanoelectronics;
  • Display technology;
  • Modeling and simulation;
  • Reliability and yield;
  • Device characterization;
  • Circuit-device interaction;
  • Energy harvesting;
  • Biomedical devices;
  • Power devices;
  • Packaging;
  • Novel materials and devices;
  • Technology roadmaps;
Engineering education.Location: Brasilia was constructed between 1956 and 1960 and inaugurated, as the new Brazilian Capital, in April 21, 1960. Its master plan ("Plano Piloto") was conceived by Lucio Costa, and its major buildings were designed by Oscar Niemeyer. Known internationally for the modernity of its architecture and urban design in the shape of an airplane (or a bird, as Lucio Costa conceived it), Brasilia has been declared by the UNESCO as "World Heritage Site". The city and its District are located in the Central-West region of the country, along a plateau known as Planalto Central.

General Chair
Ricardo Jacobi
UnB - Brazil
jacobi@unb.br

Program Chairs
Gilson Wirth
UFRGS - Brazil
wirth@inf.ufrgs.br

Dragica Vasileska
ASU - USA
vasileska@asu.edu

Local Arrangement Chairs
Carlos Llanos, UnB - Brazil
llanos@unb.br

Tutorials Chair
Henry Boudinov, UFRGS - Brazil

Panels Chair
Sérgio Bampi, UFRGS - Brazil

Finance Chair
Sandro Haddad, UnB - Brazil

Publicity Chair
Jacobus Swart, UNICAMP - Brazil

Publication Chair
Nilton Morimoto, USP - Brazil
Fernanda Kastensmidt, UFRGS - Brazil

Industry Liaison
Saulo Finco, CTI - Brazil
Jones Yudi, UnB - Brazil

Europe Liaison
Patrick Verdonk, IMEC - BE

US Liaison
Fernando Guarin, IBM - USA

LA Liaison
Mariano Aceves, INAOE - MX

Mar 20, 2012

SWOT Analysis of the Technology/Design Ecosystem", Lausanne, 30-31 May 2012

NANO-TEC Workshop 3; SWOT Analysis of Technology-Design Ecosystem: The event is part of the Coordination Action funded by the FP7 under the ICT theme, titled “ECOSYSTEMS TECHNOLOGY and DESIGN for NANOELECTRONICS” (NANO-TEC). The project started on 1 September 2010 and it aims at identifying the emerging generation of device concepts and technologies for ICT, as well as to build a joint technology-design community in order to coordinate research efforts in nanoelectronics in the European research area. 
The third workshop will tackle the topics of Solid-state quantum computing, Molecular Electronics, Nanowires, Spintronics, Graphene, MEMS and Neuromorphic Computing; finally, a panel discussion on the bridge in design from technology to application will close the event. All this will lead to the preparation of the fourth and final NANO-TEC workshop, to take place in Autumn 2012, which will provide a set of recommendations on the most promising devices and technologies identified and for future technology-design integration. In preparation for the workshop you can now join the forum available online at the following link: 

BSIMCMG is now the CMC industry standard FinFET SPICE model.

BSIMCMG is now the first industry standard FinFET SPICE model. It is available for download and use at the BSIM website. The voting took place in Jan'12 and the model was approved a standard at the March 1Q12 Osaka CMC Meeting. The CMC is yet to update their website.