[C4P] SBCCI 2025

 SBCCI2025

WWW.SBCCI.ORG.BR

SBC/SBMicro/IEEE 38th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN

August 25 to 29, 2025, Manaus, BRAZIL

CHIP IN THE JUNGLE

CALL FOR PAPERS

SBCCI is an international forum dedicated to integrated circuits and systems design, test and electronic design automation (EDA), held annually in Brazil. The 38th SBCCI will take place in Manaus, State of Amazon, Brazil. The goal of the symposium is to bring together researchers in the areas of EDA, design and test of integrated circuits and systems. The scope of the symposium includes technical sessions, tutorials and panels, as well as an exhibition and working group meetings. The proceedings will be published by the IEEE Xplore. Manuscripts must contain a maximum of 4 pages, with one additional optional 5th page containing only references. The manuscripts should follow the IEEE two-column, US-Letter format and be prepared for double-blind review. The program committee will not consider submissions of manuscripts previously published by other conferences or journals. The best papers presented at the symposium will be invited to resubmit an extended version to be considered for publication at the IEEE Design & Test and at the JICS (Journal of Integrated Circuits and Systems). Information about paper submission are available at the conference webpage.

The areas of interest include:

• System level modeling and synthesis
• High-level and logic synthesis
• Physical design of ICs and systems
• EDA – electronic design automation
• Analog, digital, and mixed signal design
• Low power tools and design techniques
• Embedded systems and cyber-physical systems design
• System-on-chip, IP reuse and platform-based design
• Verification, simulation, emulation, and prototyping techniques
• Reconfigurable architectures and novel applications of FPGAs
• Nanoelectronics, nanoarchitectures and nanocomputing
• Hardware-software co-design and co-verification
• Design and modeling languages and applications
• Testability issues, design for test techniques

Important Dates:

• Paper Submission Deadline: March 31, 2025
• Notification of Acceptance: May 20, 2025
• Camera-Ready Deadline: June 10, 2025

Sponsored by:

SBC - Brazilian Computer Society
SBMicro - Brazilian Microelectronics Society
IEEE Circuits & Systems Society
IEEE CEDA - Council on EDA

Co-Sponsored by:

IFIP WG10.5 - International Federation for Information Processing

Organized by:

UEA - Universidade do Estado do Amazonas
UFRGS - Universidade Federal do Rio Grande do Sul

Organizing Committee

General Chairs

Edgard L. O. Silva, UEA, Brazil

Ricardo Reis, UFRGS, Brazil

Program Chairs

Cristina Meinhardt, UFSC, Brazil

Gracieli Posser, Cadence, USA

Tutorial Chairs

Jose de La Rosa, CNM, Spain

André Mariano, UFPR, Brazil

Finance Chairs

Raimundo Correa de Oliveira, UEA, Brazil

Paulo Butzen, UFRGS, Brazil

Calebe Conceição, UFS, Brazil

Publication Chair

Claudio Diniz, UFRGS, Brazil

Publicity Chair

Fabián Olivera, CEFET-RJ, Brazil

[paper] Virtual N2 PDK

Yiying Liu , Minghui Yin , Huanhuan Zhou, Yunxia You, Weihua Zhang, Hongwei Liu, Chen Wang, Yajie Zou, and Zhiqiang Li

Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025)

DOI: 0.1109/TVLSI.2025.3529504

1 EDA Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing (CN)
2 School of Integrated Circuits, University of Chinese Academy of Sciences, Beijing (CN)
3 State Key Laboratory of Fabrication Technologies for Integrated Circuits, Beijing (CN)

Abstract: Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the dominant devices in sub-5-nm processes. To encourage further research into NSFET-based integrated circuits, we present Virtual_N2_PDK, a predictive process design kit (PDK) for 2-nm NSFET technology. All assumptions are based on publicly available sources. Ruthenium (Ru) interconnects are employed for the buried power rail (BPR) and tight-pitch layers. Wrap-around contact (WAC) is also integrated into Virtual_N2_PDK to investigate its impact on circuit performance. By calibrating the BSIM-CMG model with 3-D technology computer-aided design (TCAD) electrothermal simulation results, SPICE models that account for self-heating effects (SHEs) are generated for devices with and without WAC. The simulation results show that with the WAC structure, the energy-delay product (EDP) of standard cells is reduced by an average of 25.18%, while the frequency of a 15-stage ring oscillator circuit increases by 26.05%.

FIG: 3D view of the NSFET structure and layouts of SRAM bit cells:
(b) 111 SRAM cell, (c) 112 SRAM cell, and (d) 122 SRAM cell.

Acknowledgements: This work was supported in part by the Strategic Priority Research Program of Chinese Academy of Sciences (CAS) under Grant XDA0330401 and in part by CAS Youth Interdisciplinary Team under Grant JCTD-2022-07.

[paper] Lambert W function for nanoscale MOSFET modeling

A. Ortiz-Conde a, V.C.P. Silva b c, P.G.D. Agopian b c, J.A. Martino b, F.J. García-Sánchez a

Some considerations about Lambert W function-based nanoscale MOSFET charge control modeling

Solid-State Electronics (2025) 109080,

DOI:10.1016/j.sse.2025.109080

a Solid-State Electronics Lab, Universidad Simón Bolívar, Caracas 1080 (VE)
b LSI/PSI/USP, Universidade de São Paulo, São Paulo (BR)
c Department of Electronic and Telecom. Eng., Universidade Estadual Paulista, São João Da Boa Vista (BR)

Abstract: The unwanted low-level doping present in supposedly undoped MOSFET channels has a significant effect on charge control and Lambert W function-based inversion charge MOSFET models, as well as on subsequent drain current models. We show that the hypothetical intrinsic MOSFET channel approximation, often used to describe a nominally undoped channel, produces significant errors, even for the low-level concentrations resulting from unintentional doping. We show that the traditional charge control model, which mathematically describes the gate voltage as the sum of one linear and one logarithmic term of the inversion charge, is only valid for the hypothetically intrinsic case. However, it may still be used for nominally undoped but unintentionally low-doped channel devices within the region of operation where the majority carriers are the dominant charge. With this in mind, we present here a better approximation of the nominally undoped MOSFET channel surface potential. We also propose an improved, modified expression that describes the gate voltage as the sum of one linear and two logarithmic terms of the inversion charge. A new approximate drain current control formulation is also proposed to account for parasitic series resistance and/or mobility degradation. The new model agrees reasonably well with measurement data from nominally undoped vertically stacked GAA Si Nano Sheet MOSFETs.

FIG: The simulated transistor structural geometry and transfer characteristics of the three TCAD simulated nanosheet devices (symbols), together with the corresponding playbacks (lines) of the traditional model and modified model.

Data availability: Data will be made available on request.

[paper] FDSOI CMOS Cryogenic SPICE Models

P. Chava1, H. Alius2, J. Bühler1, A. R. Cabrera-Galicia1, C. Degenhardt1, T. Gneiting2, M. Harff1, T. Heide3, P. Javorka4, M. Lederer5, S. Lehmann4, M. Simon5, M. Su2, P. Vliex1, S. van Waasen1,6, C. Witt7, D. Zetzsche3

Evaluation of Cryogenic Models for FDSOI CMOS Transistors

16th IEEE Workshop on Low Temperature electronics, IEEE WOLTE16, Cagliari, Italy, Jun. 3-6, 2024

DOI: 10.34734/FZJ-2024-05369

1 Central Institute of Engineering (ZEA-2), Forschungszentrum Jülich GmbH, 52428, Jülich, (D)
2 AdMOS GmbH, 72636 Frickenhausen, (D)
3 Raycics GmbH, 01069 Dresden, (D)
4 GlobalFoundries, 01109, Dresden, (D)
5 Fraunhofer Institute for Photonic Microsystems IPMS, Center Nanoelectronic Technologies (CNT), 01109, Dresden, (D)
6 Faculty of Engineering, Communication Systems, University Duisburg-Essen, 47057 Duisburg, (D)
7 GlobalFoundries, Kapeldreef 75, 3001 Leuven, (B)

Abstract: Scalable quantum computers demand innovative solutions for tackling the wiring bottleneck to control an increasing number of qubits. Cryogenic electronics based on CMOS technologies are promising candidates which can operate down to deep-cryogenic temperatures and act as a communication and control interface to the quantum layer [1,2]. However, the performance of transistors used in these circuits is altered significantly when cooling from room temperature to cryogenic temperatures, which motivates accurate cryogenic modeling of transistors. We will report on cryogenic models tailored specifically for fully depleted silicon-on-insulator (FDSOI) transistors. We performed extensive DC characterization of transistors with subsequent modeling using the BSIM-IMG 102-9.6 model, which is the first version with a built-in cryogenic extension [3]. The preliminary models effectively represent the DC device behavior from 7 K up to room temperature. These models are used in industry standard EDA and simulation software, like Cadence Spectre. With the presented cryogenic models, we will show simulations at cryogenic temperatures. We will also compare the simulation results with the measured performance of a test chip in the temperature range from 7 K up to room temperature.

FIG: Measured and modeled transfer characteristics of a short-channel nMOST at T = 7 K

with measurement setup inside the cryogenic chamber  

Acknowledgements: This work was funded by the German Federal Ministry of Education and Research (BMBF), funding program “Quantum technologies - from basic research to market”, project QSolid (Grant No. 13N16149).

En hommage à Stefan Alexandru Cserveny