Mar 21, 2022

Build Your Own #OpenSource #Handheld #Linux PC with Raspberry Pi



from Twitter https://twitter.com/wladek60

March 21, 2022 at 05:34PM
via IFTTT

Andy Grove: Refugee, Tech Pioneer And Immigrant Entrepreneur



from Twitter https://twitter.com/wladek60

March 21, 2022 at 09:13AM
via IFTTT

Mar 18, 2022

Tso-Ping Ma (1945−2021)



from Twitter https://twitter.com/wladek60

March 18, 2022 at 09:04PM
via IFTTT

Transistor qubits heat up - Nature Electronics, Published online: 18 March 2022; doi:10.1038/s41928-022-00736-8 https://t.co/TpDZiVWvCH #semi https://t.co/8EFVKCIjsD



from Twitter https://twitter.com/wladek60

March 18, 2022 at 08:52PM
via IFTTT

[paper] Compound-Semiconductor Memory on Silicon

Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli,
Richard Beanland, and Manus Hayne
ULTRARAM: A Low-Energy, High-Endurance, 
Compound-Semiconductor Memory on Silicon 
Adv. Electron. Mater. 2022, 2101103
DOI: 10.1002/aelm.202101103
  
Department of Physics, University of Warwick (UK)


Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.
Fig: ULTRARAM device concept. a) Schematic cross-section of a device with corresponding material layers. The floating gate (FG), triple-barrier resonant-tunneling structure (TBRT), and readout channel are highlighted. Arrows indicate the direction of electron flow during program/ erase operations. b) Scanning electron micrograph of a fabricated device of 10 µm gate length. 

Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.