#top10 Hottest Semiconductor #Startups Of #2020 https://t.co/wIJrk3NU6b #semi
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November 29, 2020 at 08:50PM
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Nov 29, 2020
#top10 Hottest Semiconductor #Startups Of #2020
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Nov 28, 2020
[paper] How Objective is Peer Review?
By Hannah Bast
November 18, 2020
In 2014, the organizers of the Conference on Neural Information Processing Systems (NeurIPS, then still called NIPS) made an interesting experiment.1 They split their program committee (PC) in two and let each half independently review a bit more than half of the submissions. That way, 10% of all submissions (166 papers) were reviewed by two independent PCs. The aimed at acceptance rate per PC was 23%. The result of the experiment was that among these 166 papers, the set of accepted papers from the two PCs overlapped by only 43%. That is, more than half of the papers accepted by one PC were rejected by the other. This led to a passionate flare-up of the old debate of how effective or random peer-reviewing really is and what we should do about it. [read more...]
My bottom line: The reputation of the peer review process is tarnished. Let us work on this with the same love and attention we give to our favorite research problems. Let us do more experiments to gain insights that help us make the process more fair and regain some trust. And let us create powerful incentives, so that whatever we already know is good is actually implemented and carried over from one PC to the next.
References:
1 https://cacm.acm.org/blogs/blog-cacm/181996-the-nips-experiment provides a short description of the NIPS experiment and various links to further analyses and discussions.
2 https://github.com/ad-freiburg/esa2018-experiment
3 There are other experiments, like the single-blind vs. double-blind experiment at WSDM'17, which investigated a particular aspect of the reviewing process: https://arxiv.org/abs/1702.00502
Nov 27, 2020
#Brazilian Senate approves #tax exemption for #IoT devices
#Brazilian Senate approves #tax exemption for #IoT devices | ZDNet https://t.co/TYKRem4tcR#semi
— Wladek Grabinski (@wladek60) November 27, 2020
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November 27, 2020 at 05:40PM
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£20m for Turing Fellowships
£20m for Turing Fellowships:
New Turing #AI Acceleration #Fellowships will give fifteen of the UK’s top AI innovators the resources to drive forward research from speeding up medical diagnosis to increasing workplace productivity. https://t.co/9nIjr67rwE#semi pic.twitter.com/9opCVAFWGi
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[paper] Trillion-transistor chip breaks speed record
Kamil Rocki∗, Dirk Van Essendelft†, Ilya Sharapov∗, Robert Schreiber∗, Michael Morrison∗, Vladimir Kibardin∗, Andrey Portnoy∗, Jean Francois Dietiker†‡, Madhava Syamlal†
and Michael James∗
Fast Stencil-Code Computation on a Wafer-Scale Processor
Online SC20 Supercomputing Conference
arXiv:2010.03660 [cs.DC] (2020)
∗ Cerebras Systems Inc., Los Altos, California, USA
† National Energy Technology Laboratory, Morgantown, West Virginia, USA
‡ Leidos Research Support Team, Pittsburgh, Pennsylvania, USA
Abstract: The performance of CPU-based and GPUbased systems is often low for PDE codes, where large, sparse, and often structured systems of linear equations must be solved. Iterative solvers are limited by data movement, both between caches and memory and between nodes. Here we describe the solution of such systems of equations on the Cerebras Systems CS-1, a wafer-scale processor that has the memory bandwidth and communication latency to perform well. We achieve 0.86 PFLOPS on a single wafer-scale system for the solution by BiCGStab of a linear system arising from a 7-point finite difference stencil on a 600 × 595 × 1536 mesh, achieving about one third of the machine’s peak performance. We explain the system, its architecture and programming, and its performance on this problem and related problems. We discuss issues of memory capacity and floating point precision. We outline plans to extend this work towards full applications.
Fig: CS-1 Wafer Scale Engine (WSE). A single wafer (rightmost) contains one CS-1 processor. Each processor is a collection of dies arranged in a 2D fashion (middle). Dies are then further subdivided into a grid of tiles. One die hosts thousands of computational cores, memory and routers (leftmost). There is no logical discontinuity between adjacent dies and there is no additional bandwidth penalty for crossing the die-die barrier. In total, there are 1.2 trillion transistors in an area of 462.25 cm2.
Acknowledgement: The authors would like to thank Natalia Vassilieva for initiating the collaboration between Cerebras Systems and NETL and for her subsequent help with the project.
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