[paper] Vectorizing Device Model Evaluation in Ngspice

Vectorizing Device Model Evaluation in Ngspice circuit simulator

Florian Ballenegger, Anamosic Ballenegger Design

Preprint July 2020

Abstract: A method improving the execution speed of electrical circuit simulation using vector processing is proposed. The BSIM3V32 semi-conductor device model for the open-source Ngspice simulator has been re-written for evaluating multiple device instances of the same model at once using Single Instruction Multiple Data (SIMD) processor instructions. While parallel evaluation of device model was already available using multiprocessing, the proposed method can achieve the same speed-up using less processor resources, thus allowing to do more parallel independent simulations for statistical analysis.

In Conclusion: Only the BSIM3V32 device model was modified to use vector processing. Other device models would of course also benefit from the proposed method. In particular interest would be the EKV model https://github.com/ekv26/model, as the calculations in this symmetric model are more linear with fewer conditional branches and could be vectorized more efficently.  The source code of the modified BSIM3V3 model is available at https://www.anamosic.com/pages/ngspice.html

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U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ #semi https://t.co/Zxeyxds702

U.S. Senators C.Schumer and K.Gillibrand pushed through a massive semiconductor manufacturing incentive package worth as much as $25 #billion that could benefit #GF and #IBM, both are in the Capital Region and the Hudson Valley.https://t.co/lah21UaJsZ#semi pic.twitter.com/Zxeyxds702

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[paper] Symmetric Source and Drain Voltage Clamping Scheme

K. Xia¹ (Senior Member, IEEE)

Symmetric Source and Drain Voltage Clamping Scheme

for Complete Source-Drain Symmetry in Field-Effect Transistor Modeling

in IEEE Transactions on Electron Devices

DOI: 10.1109/TED.2020.3004799

¹NXP Semiconductors N.V., Chandler, AZ 85224 USA

Abstract: For structurally symmetric field-effect transistors with respect to the source and the drain, their models should be electrically symmetric about the source-drain interchange. This article shows that the commonly used drain-source voltage clamping technique breaks such a symmetry. This article then presents a symmetric source and drain voltage clamping scheme to solve the problem. The effectiveness of the new scheme is demonstrated by both the planar MOSFET model PSP and the FinFET model BSIM-CMG.

Fig: Fourth order derivative of I_x with respect to V_x during Gummel symmetry test for an n-MOSFET on a 130nm technology. V_g = 1.15V. Vb = 0V. W/L = 10.02μm/0.15μm. V_d = −V_s = V_x. T=27^◦C. V_x stepsize is 10mV in the measurement and 0.1mV in the simulation, respectively.