#EMM to offer its ultra low power 180nm #CMOS for #MPW service https://t.co/beBG061h9y #model https://t.co/6MOVGvrX97

#EMM to offer its ultra low power 180nm #CMOS for #MPW service https://t.co/beBG061h9y #model pic.twitter.com/6MOVGvrX97

— Wladek Grabinski (@wladek60) March 4, 2019

from Twitter https://twitter.com/wladek60

March 04, 2019 at 10:26PM
via IFTTT

F. Jazaeri and J. Sallese, "Charge-Based EPFL HEMT #Model," in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1218-1229, March 2019. https://t.co/rFwjVUuRbM

F. Jazaeri and J. Sallese, "Charge-Based EPFL HEMT #Model," in IEEE Transactions on Electron Devices, vol. 66, no. 3, pp. 1218-1229, March 2019. https://t.co/rFwjVUuRbM

— Wladek Grabinski (@wladek60) March 1, 2019

from Twitter https://twitter.com/wladek60

March 01, 2019 at 02:15PM
via IFTTT

IIT Kanpur: open compact modeling position

Indian Institute of Technology, Kanpur

The Office of Research & Development

Date: 15-02-2019

Indian Institute of Technology, Kanpur an Institute of national importance, has been in the forefront of engineering & technology education and research & development. The Institute derives strength from its philosophy, vision and values that has led to achievement of academic excellence and promotion of high order technological research. The Institute's R&D Division is looking for suitable Indian nationals including Persons of Indian Origins (PIOs) and Overseas Citizens of India (OCIs) for appointment on the following positions for short-term R&D Projects on contractual basis for a period of maximum five years.

Please forward this job opening with following requirements to your friends/colleagues.

http://iitk.ac.in/new/RnD_Recruitment/

• Hands-on experience of I-V (DC and Pulsed), CV, RF (CW and Pulsed)
• Expertise in Semiconductor Device Modeling and Simulation softwares
• PDK Development & Layout design
• Knowledge of Verilog-A language, PEL/ Python script.
• Strong background in semiconductor device physics
• Good writing skills
• Good Project Management skills

#FOSDEM 2019 – Space and Meaning https://t.co/mQqeuvwtrN #paper

#FOSDEM 2019 – Space and Meaning https://t.co/mQqeuvwtrN #paper

— Wladek Grabinski (@wladek60) February 17, 2019

from Twitter https://twitter.com/wladek60

February 17, 2019 at 10:45PM
via IFTTT

[mos-ak] 2019 IEEE International Conference on Modeling of Systems Circuits and Devices

2019 IEEE International Conference on Modeling of Systems Circuits and Devices

(MOS-AK/India 2019)

Organized by Joint Chapters of CAS / EDS Societies

IEEE Hyderabad Section

Together with the lead sponsors and the conference organization committee we have pleasure to invite to consecutive, 2nd MOS-AK/India Compact Modeling Conference to be hosted at the IIT Hyderabad

Announced, subsequent 2nd MOS-AK/India Conference organized at the IIT Hyderabad, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <http://www.mos-ak.org/india_2019/>

Dates:

MOS-AK/India Conference - February 25-27, 2019

Feb. 25      - ONE day SPICE/Verilog-A Modeling Tutorials

Feb. 26-27 - TWO days SPICE/Verilog-A Modeling Conference

Venue:

Indian Institute of Technology (IIT)

Hyderabad, Kandi

Telangana State, India

Online registration (any related enquiries can be sent secretary.mosak.india@gmail.com or call 9652158557) 

W.Grabinski on the behalf of International MOS-AK Committee

WG02092019

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