Characterization and #Modeling of Temperature Effects in #3D #NAND Flash Arrays—Part II: Random Telegraph #Noise https://t.co/gQUJCnoP3O

Characterization and #Modeling of Temperature Effects in #3D #NAND Flash Arrays—Part II: Random Telegraph #Noise https://t.co/gQUJCnoP3O

— Wladek Grabinski (@wladek60) July 24, 2018

from Twitter https://twitter.com/wladek60

July 24, 2018 at 05:13PM
via IFTTT

A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8 https://t.co/68fIGLy7M8

A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8 https://t.co/68fIGLy7M8

— Wladek Grabinski (@wladek60) July 24, 2018

from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
via IFTTT

A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8

A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8

— Wladek Grabinski (@wladek60) July 24, 2018

from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
via IFTTT

[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018

MOS-AK Workshop at ESSDERC/ESSCIRC

http://www.mos-ak.org/dresden_2018/

Dresden, Sept. 3, 2018

Subsequent MOS-AK modeling workshop organized at ESSDERC/ESSCIRC in Dresden on Sept. 3, 2018, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:

<http://www.mos-ak.org/dresden_2018/>

Venue:

Technische Universität Dresden

room CHE/0184/U

Dresden (D)

Agenda:

• MOS-AK Workshop: Sept. 3, 2018
• ESSDERC Track4 "Compact modeling of devices and circuit" Sept. 5-6, 2018
• Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
  Chair: Wladek Grabinski, Thierry Poiroux
• Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
  Chair: Daniel Tomaszewski, Benjamin Iniguez

Online Workshop Registration is still open

(any related inquiries can be sent to registration@mos-ak.org)

Postworkshop Publications:

Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

International MOS-AK Committee

WG180718

 

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SINANO Modelling Summer School in Tarragona (Spain): Registration Open!

The 8th SINANO Modelling Summer School will take place in Tarragona (Catalonia, Spain) from September 25 to 28 2018, co-organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. It is also partially sponsored by the SINANO Institute and the DOMINO EU H2020 project.

The official website of the SINAMO Modelling Summer School is:

http://wwwa.fundacio.urv.cat/congressos/sinano-modelling-summer-school/

REGISTRATION IS ALREADY OPEN. The SINANO Modeling Summer School extended deadline for the reduced fee registration is now: September 12.

The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 6th Framework Programme of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy  (2016, 2014, 2012, 2010, 2008, 2006).

The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world’s leading device simulation and electrical characterization experts.

This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices. It includes a total of 23 lectures targeting topics related to the modelling, simulation and characterization of diferent types of semiconductor devices for nanoelectronics, flexible electronics and photonics. Very hot topics, such as devices for quantum computing, neuromorphic computing, THz electronics and printed electronics will also be addressed. The lecturers are internationally well recognized experts in these fields. Our SINANO Summer School is a unique opportunity for young researchers to become familiar with all scales of device modelling and for many types of device structures, as well as to interact with those top researchers.

THE PROGRAMME HAS ALREADY BEEN PUBLISHED.

http://wwwa.fundacio.urv.cat/congressos/public/usr_docs/program_sinanosummer_schoolupdated_3_7.pdf

Invited speakers' short biographies are given in:

http://wwwa.fundacio.urv.cat/congressos/sinano-modelling-summer-school/invited-speakers

Apart from the technical programme, we include a social program consisting of a Welcome Reception and a Gala Dinner in a nice place in front of the Mediterranean Sea. And I hope you can find some time to walk down Tarragona streets and see its main landmarks, many of them dating back to the Roman Empire. Besides, September 23 is Tarragona Patron Saint Day (“Santa Tecla”), and around that date there will be many nice celebrations and musical performances in the city.

Therefore, I encourage researchers in semiconductor device technology, modeling and circuit design to attend this 8^th SINANO Modelling Summer School,a.