* Dec.9, 2009
* collocated with
o IEDM Conference (Dec.6-9 <http://www.his.com/~iedm/general/
schedule.html>)
o CMC Meeting (Dec.10-11<http://www.geia.org/index.asp?
bid=597>)
Location:
* Johns Hopkins University at Homewood Campus in the Computational
Sciences and Engineering
o Building (CSEB) Room CSEB 17
o free on-line registration
o http://www.mos-ak.org/baltimore/register.php
o General visitor information for JHU
o http://webapps.jhu.edu/jhuniverse/information_about_hopkins/visitor_information/
o Map of the campus
o http://www.mos-ak.org/baltimore/campus_map_0907.pdf
Audience:
* about 50+ (similar to http://mos-ak.org/sanfrancisco/)
* 6-8 invited noted speakers presenting academia and industry
o plus a poster session
* panel discussion at the end of the workshop
o Compact models QA validation: Still a challenge?
Synopsis:
* HiTech forum to discuss the frontiers of the compact/spice
modeling
* MOS-AK/GSA Meetings are organized with aims to strengthen a
network and discussion forum among experts in the field, enhance open
platform for information exchange related to compact/Spice modeling,
bring people in the compact modeling field together, as well as obtain
feedback from technology developers, circuit designers, and CAD tool
vendors. The topics cover all important aspects of compact model
development, implementation, deployment and standardization within the
main theme - frontiers of the compact modeling for nm-scale CMOS/SOI
circuit simulation.
* The specific workshop goal will be to classify the most
important directions for the future development of the compact models
and to clearly identify areas that need further research. This
workshop is designed for device process engineers (CMOS, SOI, BiCMOS,
SiGe) who are interested in device modeling; ICs designers (RF/Analog/
Mixed-Signal/SoC) and those starting in that area as well as device
characterization, modeling and parameter extraction engineers. The
content will be beneficial for anyone who needs to learn what is
really behind the IC simulation in modern device models.
Program:
* Topics (open list):
o electronic abstracts submission
o http://www.mos-ak.org/baltimore/abstracts.php
* Advanced MOST compact models for the bulk/SOI and compound
technologies
* Alternative models for analog/RF and HV applications
* High level behavioral languages (Verilog/VHDL) for compact
models standardization
* CAD tools for model implementation
* Parameter extraction, model QA and lib generation and validation
* GNU/open source software support
Speakers:
* I. Angelov: "Fundamentals of FET Device Modelling for GaN, SiC,
GaAs and CMOS"
* A.G. Andreou: TBD
* G. Coram: "Verilog-A standardization and model validation"
* B. Iniguez: "COMON: EU compact modeling project"
* J. J. Liou: TBD
* M. Mierzwinski: "Practical Considerations for Developing,
Debugging, and Releasing Verilog-A Models"
* C.G. Montoro: "CMOS Analog Design Using All-Region MOSFET
Modeling"
* M. Reece: TBD
* J. Victory: TBD
Publication:
* The MOS-AK presentation will be available on-line after the
event
* Selected papers will be recommended for further publications
o Solid-State Electronics
o International Journal of Numerical Modeling
Committee:
* Andreas G. Andreou, JHU; Technical Program Chair
* Pekka Ojala, Exar; MOS-AK/GSA WG North America Chair
* Gilson I Wirth; UFRGS; MOS-AK/GSA WG South America Chair
* Ehrenfried Seebacher, austriamicrosystems AG; MOS-AK/GSA WG
Europe Chair
* Al Kordesch, Silterra Malaysia; MOS-AK/GSA WG Asia/Pacific Chair
* Chelsea Boone GSA; Senior Research Analyst
* Darryl Leavitt, GSA; Director of Events
* Wladek Grabinski, GMC Suisse; MOS-AK/GSA Workshop Manager
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