Google moves #AndroidX to the Android #OpenSource Project https://t.co/DJ6ND6qErz pic.twitter.com/xpXdAD48uc
— Wladek Grabinski (@wladek60) July 30, 2018
from Twitter https://twitter.com/wladek60
July 30, 2018 at 11:44PM
via IFTTT
Jul 30, 2018
Google moves #AndroidX to the Android #OpenSource Project https://t.co/DJ6ND6qErz https://t.co/xpXdAD48uc
from Twitter https://twitter.com/wladek60
July 30, 2018 at 11:44PM
via IFTTT
#10top reasons for #entrepreneurs to love #opensource software https://t.co/D9NuYwN7x4 https://t.co/keJFoD3L4g
#10top reasons for #entrepreneurs to love #opensource software https://t.co/D9NuYwN7x4 pic.twitter.com/keJFoD3L4g
— Wladek Grabinski (@wladek60) July 30, 2018
from Twitter https://twitter.com/wladek60
July 30, 2018 at 06:08PM
via IFTTT
Jul 27, 2018
How an #opensource education can #help #students gain an edge https://t.co/UvbXeehXls https://t.co/C8jS9N94Fs
How an #opensource education can #help #students gain an edge https://t.co/UvbXeehXls pic.twitter.com/C8jS9N94Fs
— Wladek Grabinski (@wladek60) July 27, 2018
from Twitter https://twitter.com/wladek60
July 27, 2018 at 11:01AM
via IFTTT
Jul 26, 2018
#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper
#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper
— Wladek Grabinski (@wladek60) July 26, 2018
from Twitter https://twitter.com/wladek60
July 26, 2018 at 09:49PM
via IFTTT
#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper
#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper
— Wladek Grabinski (@wladek60) July 26, 2018
from Twitter https://twitter.com/wladek60
July 26, 2018 at 09:20PM
via IFTTT
#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper
#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper
— Wladek Grabinski (@wladek60) July 26, 2018
from Twitter https://twitter.com/wladek60
July 26, 2018 at 09:49PM
via IFTTT
#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper
#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper
— Wladek Grabinski (@wladek60) July 26, 2018
from Twitter https://twitter.com/wladek60
July 26, 2018 at 09:20PM
via IFTTT
Jul 25, 2018
Electrical #contact to #molecules in #semiconductor structures established for the first time https://t.co/s4JvZCyvcL #paper
Electrical #contact to #molecules in #semiconductor structures established for the first time https://t.co/s4JvZCyvcL #paper
— Wladek Grabinski (@wladek60) July 24, 2018
from Twitter https://twitter.com/wladek60
July 24, 2018 at 11:12PM
via IFTTT
Jul 24, 2018
Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1 https://t.co/T4cI4ySoH1
Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1 https://t.co/T4cI4ySoH1
— Wladek Grabinski (@wladek60) July 24, 2018
from Twitter https://twitter.com/wladek60
July 24, 2018 at 09:18PM
via IFTTT
Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1
Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1
— Wladek Grabinski (@wladek60) July 24, 2018
from Twitter https://twitter.com/wladek60
July 24, 2018 at 09:18PM
via IFTTT
Characterization and #Modeling of Temperature Effects in #3D #NAND Flash Arrays—Part II: Random Telegraph #Noise https://t.co/gQUJCnoP3O
Characterization and #Modeling of Temperature Effects in #3D #NAND Flash Arrays—Part II: Random Telegraph #Noise https://t.co/gQUJCnoP3O
— Wladek Grabinski (@wladek60) July 24, 2018
from Twitter https://twitter.com/wladek60
July 24, 2018 at 05:13PM
via IFTTT
A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8 https://t.co/68fIGLy7M8
A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8 https://t.co/68fIGLy7M8
— Wladek Grabinski (@wladek60) July 24, 2018
from Twitter https://twitter.com/wladek60
July 24, 2018 at 10:12AM
via IFTTT
A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8
A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8
— Wladek Grabinski (@wladek60) July 24, 2018
from Twitter https://twitter.com/wladek60
July 24, 2018 at 10:12AM
via IFTTT
Jul 18, 2018
[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018
MOS-AK Workshop at ESSDERC/ESSCIRC
Dresden, Sept. 3, 2018
Subsequent MOS-AK modeling workshop organized at ESSDERC/ESSCIRC in Dresden on Sept. 3, 2018, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:
Venue:
Technische Universität Dresdenroom CHE/0184/UDresden (D)
Agenda:
- MOS-AK Workshop: Sept. 3, 2018
- ESSDERC Track4 "Compact modeling of devices and circuit" Sept. 5-6, 2018
- Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
Chair: Wladek Grabinski, Thierry Poiroux - Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
Chair: Daniel Tomaszewski, Benjamin Iniguez
Online Workshop Registration is still open
(any related inquiries can be sent to registration@mos-ak.org)
Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems
in a special issue of the International Journal of High Speed Electronics and Systems
WG180718
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Jul 11, 2018
SINANO Modelling Summer School in Tarragona (Spain): Registration Open!
The 8th SINANO Modelling Summer School
will take place in Tarragona (Catalonia, Spain) from September 25 to 28
2018, co-organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. It is also partially sponsored by the SINANO Institute and the DOMINO EU H2020 project.
The official website of the SINAMO Modelling Summer School is:
REGISTRATION IS ALREADY OPEN. The SINANO Modeling Summer School extended deadline for the reduced fee registration is now: September 12.
The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 6th Framework Programme of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy (2016, 2014, 2012, 2010, 2008, 2006).
The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world’s leading device simulation and electrical characterization experts.
This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices. It includes a total of 23 lectures targeting topics related to the modelling, simulation and characterization of diferent types of semiconductor devices for nanoelectronics, flexible electronics and photonics. Very hot topics, such as devices for quantum computing, neuromorphic computing, THz electronics and printed electronics will also be addressed. The lecturers are internationally well recognized experts in these fields. Our SINANO Summer School is a unique opportunity for young researchers to become familiar with all scales of device modelling and for many types of device structures, as well as to interact with those top researchers.
The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 6th Framework Programme of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy (2016, 2014, 2012, 2010, 2008, 2006).
The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world’s leading device simulation and electrical characterization experts.
This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices. It includes a total of 23 lectures targeting topics related to the modelling, simulation and characterization of diferent types of semiconductor devices for nanoelectronics, flexible electronics and photonics. Very hot topics, such as devices for quantum computing, neuromorphic computing, THz electronics and printed electronics will also be addressed. The lecturers are internationally well recognized experts in these fields. Our SINANO Summer School is a unique opportunity for young researchers to become familiar with all scales of device modelling and for many types of device structures, as well as to interact with those top researchers.
Invited speakers' short biographies are given in:
Apart from the technical programme, we
include a social program consisting of a Welcome Reception and a Gala
Dinner in a nice place in front of the Mediterranean Sea. And I hope you
can find some time to walk down Tarragona streets and see its main
landmarks, many of them dating back to the Roman Empire. Besides,
September 23 is Tarragona Patron Saint Day (“Santa Tecla”), and around
that date there will be many nice celebrations and musical performances
in the city.
Therefore, I encourage researchers in semiconductor device technology, modeling and circuit design to attend this 8th SINANO Modelling Summer School,a.
Jul 9, 2018
#OpenSource plays vital role in #scientific #advances https://t.co/yXIAJpB7OU https://t.co/y9gbdI6hwR
#OpenSource plays vital role in #scientific #advances https://t.co/yXIAJpB7OU pic.twitter.com/y9gbdI6hwR
— Wladek Grabinski (@wladek60) July 9, 2018
from Twitter https://twitter.com/wladek60
July 09, 2018 at 03:08PM
via IFTTT
Jul 5, 2018
Evaluation of #10nm Bulk #FinFET #RF Performance -Conventional vs. NC-FinFET - IEEE Journals & Magazine #paper https://t.co/dH5G1DQJCm https://t.co/dH5G1DQJCm
Evaluation of #10nm Bulk #FinFET #RF Performance -Conventional vs. NC-FinFET - IEEE Journals & Magazine #paper https://t.co/dH5G1DQJCm https://t.co/dH5G1DQJCm
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 06:46PM
via IFTTT
Evaluation of #10nm Bulk #FinFET #RF Performance -Conventional vs. NC-FinFET - IEEE Journals & Magazine #paper https://t.co/dH5G1DQJCm
Evaluation of #10nm Bulk #FinFET #RF Performance -Conventional vs. NC-FinFET - IEEE Journals & Magazine #paper https://t.co/dH5G1DQJCm
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 06:46PM
via IFTTT
Heterogeneously Integrated Impedance Based Biosensors (technology scaling on low-noise transimpedance amplifiers was studied using the Enz-Krummenacher-Vittoz (#EKV) model) https://t.co/p91Kn839bj #paper https://t.co/VWfQDyeDJy https://t.co/O8mutPeYJc
Heterogeneously Integrated Impedance Based Biosensors (technology scaling on low-noise transimpedance amplifiers was studied using the Enz-Krummenacher-Vittoz (#EKV) model) https://t.co/p91Kn839bj #paper pic.twitter.com/VWfQDyeDJy https://t.co/O8mutPeYJc
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 06:40PM
via IFTTT
Heterogeneously Integrated Impedance Based Biosensors (technology scaling on low-noise transimpedance amplifiers was studied using the Enz-Krummenacher-Vittoz (#EKV) model) https://t.co/p91Kn839bj #paper https://t.co/VWfQDyeDJy
Heterogeneously Integrated Impedance Based Biosensors (technology scaling on low-noise transimpedance amplifiers was studied using the Enz-Krummenacher-Vittoz (#EKV) model) https://t.co/p91Kn839bj #paper pic.twitter.com/VWfQDyeDJy
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 06:40PM
via IFTTT
High accuracy large-signal #SPICE model for silicon carbide (#SiC) #MOSFET https://t.co/93yZ8JEbv8 #paper
High accuracy large-signal #SPICE model for silicon carbide (#SiC) #MOSFET https://t.co/93yZ8JEbv8 #paper
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 04:27PM
via IFTTT
Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era https://t.co/vmVDYfMPcH #paper https://t.co/Lu5f4UXm47 https://t.co/G3A9t83dDd
Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era https://t.co/vmVDYfMPcH #paper pic.twitter.com/Lu5f4UXm47 https://t.co/G3A9t83dDd
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 04:26PM
via IFTTT
Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era https://t.co/vmVDYfMPcH #paper https://t.co/Lu5f4UXm47
Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era https://t.co/vmVDYfMPcH #paper pic.twitter.com/Lu5f4UXm47
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 04:26PM
via IFTTT
Toward a sustainable materials system https://t.co/Z5j8ezhTSm #paper https://t.co/MjjavPoXEv
Toward a sustainable materials system https://t.co/Z5j8ezhTSm #paper pic.twitter.com/MjjavPoXEv
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 10:46AM
via IFTTT
A bright future for microelectronics at CERN | EP Department newsletter https://t.co/QoB8YqI8KZ #paper https://t.co/ID31W3qp3Z
A bright future for microelectronics at CERN | EP Department newsletter https://t.co/QoB8YqI8KZ #paper pic.twitter.com/ID31W3qp3Z
— Wladek Grabinski (@wladek60) July 5, 2018
from Twitter https://twitter.com/wladek60
July 05, 2018 at 10:30AM
via IFTTT
Jun 30, 2018
CMOS-Integrated Low-Noise Junction Field-Effect Transistors #JFET for #Bioelectronic Applications - IEEE Journals & Magazine https://t.co/2xBWocU81z #paper https://t.co/2xBWocU81z
CMOS-Integrated Low-Noise Junction Field-Effect Transistors #JFET for #Bioelectronic Applications - IEEE Journals & Magazine https://t.co/2xBWocU81z #paper https://t.co/2xBWocU81z
— Wladek Grabinski (@wladek60) June 30, 2018
from Twitter https://twitter.com/wladek60
June 30, 2018 at 10:22PM
via IFTTT
CMOS-Integrated Low-Noise Junction Field-Effect Transistors #JFET for #Bioelectronic Applications - IEEE Journals & Magazine https://t.co/2xBWocU81z #paper
CMOS-Integrated Low-Noise Junction Field-Effect Transistors #JFET for #Bioelectronic Applications - IEEE Journals & Magazine https://t.co/2xBWocU81z #paper
— Wladek Grabinski (@wladek60) June 30, 2018
from Twitter https://twitter.com/wladek60
June 30, 2018 at 10:21PM
via IFTTT
Jun 18, 2018
2018 SINANO Modeling Summer School in Tarragona, Spain
The 8th SINANO Modeling Summer School
in Tarragona (Catalonia)
September 25 to 28 2018
The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 7th FB of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy (2016, 2014, 2012, 2010, 2008, 2006).
The Sinano Modeling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a program consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world's leading device simulation and electrical characterization experts. This year the SINANO Modeling Summer School will target multi-scale modeling of semiconductor devices.
The 7th SINANO Modeling Summer School is partially sponsored by the SINANO Institute and the DOMINO EU H2020 project. It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The Chair of the 8th SINANO Modeling Summer School is Prof. Benjamin Iñiguez, who is also the Coordinator of the DOMINO project.
Registration, with reduced fees for students, will be open soon.
The Sinano Modeling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a program consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world's leading device simulation and electrical characterization experts. This year the SINANO Modeling Summer School will target multi-scale modeling of semiconductor devices.
The 7th SINANO Modeling Summer School is partially sponsored by the SINANO Institute and the DOMINO EU H2020 project. It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The Chair of the 8th SINANO Modeling Summer School is Prof. Benjamin Iñiguez, who is also the Coordinator of the DOMINO project.
Registration, with reduced fees for students, will be open soon.
2018 SINANO Modeling Summer School Program:
Tuesday, September 25 2018
| |
8:30
|
Opening Session
Benjamin Iñiguez (Universitat Rovira i Virgili)
|
IEEE EDS MINI-COLLOQUIUM
ON SEMICONDUCTOR DEVICE MODELING | |
8:55
|
"Characterization Techniques for Ultrathin Materials and Devices".
Sorin Cristoloveanu (MINATEC, France)
|
10:05
|
"Compact Modeling of Organic Thin Film Transistors"
Jamal Deen (McMaster University, Canada)
|
11:15
|
Coffee Break
|
11:40
|
"Multiscale Reliability Modeling"
Tibor Grasser (TU-Wien, Austria)
|
12:50
|
"FOSS TCAD/EDA Tools for Compact Modeling"
Wladek Grabinski (GMC, Switzerland)
|
14:00
|
Lunch
|
SINANO MODELING SUMMER SCHOOL
| |
15:15
|
"Monte Carlo simulation of THz nanodevices based on III-V semiconductors"
Javier Mateos (University of Salamanca, Spain)
|
16:25
|
"Monte Carlo simulation of emerging Si devices"
Francisco Gámiz (University of Granada, Spain)
|
20:00
|
Welcome Reception
|
Wednesday September 26 2018
| |
9:00
|
"Steep-slope devices: prospects and challenges"
Elena Gnani (University of Bologna)
|
10:10
|
"Physics of novel devices for quantum information science"
Thierry Ferrus et al. (Hitachi Cambridge Laboratory, UK)
|
11:20
|
Coffee break
|
11:30
|
"Spiking Neural Circuits and Systems"
François Danneville (IEMN, France)
|
12:50
|
"Time Dependent Variability in CMOS devices: characterization and compact modeling"
Montserrat Nafria (Autonomous University of Barcelona, Spain)
|
14:00
|
Lunch
|
15:15
|
"Atomic-scale modeling of semiconductor technology"
Kurt Stokbro (Synopsis QuantumWise, Denmark)
|
16:25
|
"Physics and modeling of organic and hybrid photovoltaic devices"
Lluís F. Marsal (Universitat Rovira i Virgili, Spain)
|
Thursday, June 27 2018
| |
9:00
|
"Complex structure deformation simulation in TCAD for flexible electronics"
Ahmed Nejim (Silvaco Europe Ltd., UK)
|
10:10
|
"Mathematical and Semi-physical modeling for emerging device tecnologies & needs"
Firas Mohamed. (Infiniscale, France)
|
11:20
|
Coffee break
|
11:30
|
"Advanced modeling of AlGaN/GaN HEMT transistors: the ASM HEMT model"
Sourabh Khandelwal (Macquarie University, Australia)
|
12:50
|
"Electrical characterization of low frequency noise"
Thomas Gneiting (AdMOS GmbH, Germany)
|
14:00
|
Lunch
|
15:15
|
"TCAD and compact modeling of source-gated transistors"
Radu Sporea (University of Surrey, UK)
|
16:25
|
"Compact modeling of memristors"
Rodrigo Picos (Universitat de les Illes Balears, Spain)
|
20:30
|
Gala Dinner
|
Friday, September 28 2018
| |
9:00
|
"Current status and trends in RF SOI material and devices"
Jean-Pierre Raskin (Université catholique de Louvain, Belgium)
|
10:10
|
"Characterization and Modeling of Organic Diodes and TFTs""
Yvan Bonnassieux (Ecole Polytechnique, France)
|
11:20
|
Coffee break
|
11:30
|
"Mechanical Deformation-Aware Compact Modeling for Flexible Electronics"
Slobodan Mijalkovic (Silvaco Europe Ltd., UK)
|
12:50
|
"Physics and operation of sonic devices"
Giuseppe Iannaccone (University of Pisa, Italy)
|
14:00
|
Lunch
|
15:15
|
"Parameter extraction and modeling of Amorphous Oxide TFTs"
Benjamin Iñiguez (Universitat Rovira i Virgili, Spain)
|
16:25
|
Closing Session
|
I strongly encourage researchers in semiconductor devices, especially Ph D students and postdocs to attend the SINANO Modeling Summer School in Tarragona!!!
Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.
Tarragona is one of the most important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
Prof. Benjamin Iñiguez
The Chair of the 8th SINANO Modeling Summer SchoolCoordinator of the DOMINO project
Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.
Tarragona is one of the most important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
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Jun 16, 2018
2018 SINANO Modelling Summer School in Tarragona, Spain
The 8th SINANO Modelling Summer
School will take place in Tarragona (Catalonia, Spain) from September
25 to 28 2018.
The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 7th FB of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy (2016, 2014, 2012, 2010, 2008, 2006).
The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world’s leading device simulation and electrical characterization experts.
This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices.
The 7th SINANO Modelling Summer School is partially sponsored by the SINANO Institute and the DOMINO EU H2020 project.
It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The Chair of the 8th SINANO Modelling Summer School is Prof. Benjamin Iñiguez, who is also the Coordinator of the DOMINO project.
Registration, with reduced fees for students, will be open soon.
Here is updated programme:
The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 7th FB of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy (2016, 2014, 2012, 2010, 2008, 2006).
The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world’s leading device simulation and electrical characterization experts.
This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices.
The 7th SINANO Modelling Summer School is partially sponsored by the SINANO Institute and the DOMINO EU H2020 project.
It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The Chair of the 8th SINANO Modelling Summer School is Prof. Benjamin Iñiguez, who is also the Coordinator of the DOMINO project.
Registration, with reduced fees for students, will be open soon.
Here is updated programme:
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Tuesday,
September 25 2018
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8:30
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Opening
Session
Opening
Benjamin
Iñiguez (Universitat Rovira i Virgili)
IEEE
EDS MINI-COLLOQUIUM ON SEMICONDUCTOR DEVICE MODELLING
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8:55
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"Characterization
Techniques for Ultrathin Materials and Devices".
Sorin
Cristoloveanu (MINATEC, France)
|
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10:05
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"Compact
Modeling of Organic Thin Film Transistors"
Jamal Deen (McMaster
University,
Canada)
|
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11:15
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Coffee Break
|
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11:40
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"Multiscale
Reliability Modeling"
Tibor Grasser (TU-Wien, Austria)
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12:50
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"FOSS TCAD/EDA Tools for
Compact Modelling"
Wladek
Grabinski (GMC, Switzerland)
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14:00
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Lunch
SINANO
MODELLING SUMMER SCHOOL
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15:15
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"Monte Carlo simulation of
THz nanodevices based on III-V semiconductors"
Javier
Mateos (University of Salamanca,
Spain)
|
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16:25
20:00
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“Monte Carlo simulation of
emerging Si
devices”
Francisco Gámiz (University of
Granada,
Spain)
Welcome Reception
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Wednesday
September 26 2018
|
|
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9:00
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"Steep-slope
devices: prospects and challenges"
Elena
Gnani (University of Bologna)
|
|
10:10
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"Physics
of novel devices for quantum information science"
Thierry
Ferrus et al. (Hitachi Cambridge Laboratory, UK)
|
|
11:20
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Coffee break
|
|
11:30
|
“Spiking
Neural Circuits and Systems”
François
Danneville (IEMN, France)
|
|
12:50
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"Time
Dependent Variability in CMOS devices: characterization and compact
modelling"
Montserrat
Nafria (Autonomous University of Barcelona, Spain)
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14:00
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Lunch
|
|
15:15
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“Atomic-scale
modelling of semiconductor technology"
Kurt Stokbro (Synopsis
QuantumWise, Denmark)
|
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16:25
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"Physics and modelling of
organic and hybrid photovoltaic devices"
Lluís F.
Marsal (Universitat Rovira i
Virgili, Spain)
Thursday,
June 27 2018
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|
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I strongly encourage
researchers in semiconductor devices, especially Ph D students and
postdocs to attend the SINANO Modelling Summer School in Tarragona!!!
Tarragona
is about 100 Km south from Barcelona, on the coast (the so-called "Costa
Daurada",
Golden Coast). Traveling to Tarragona from Barcelona is easier. There
are frequent direct buses between Tarragona and Barcelona Airport, and
also frequent trains between Tarragona and Barcelona. Besides, from
some
European cities it is possible to fly to Reus Airport, which is about
10 Km from Tarragona.
Tarragona
is one of the most important hubs of tourism in Europe, not
only because of the nice beaches around the city, but also because of
its historical landmarks.. Tarragona was a very important city of the
Roman Empire. In 2000 UNESCO committee officially declared the Roman
archaeological complex of Tarraco (name of Tarragona during the Roman
Empire) a World Heritage Site. This
recognition is intended to help ensure the conservation of the
monuments, as well as to introduce them to the broader international
public.
#Integrated, short-open-load-through (#SOLT) cable/antenna calibration kits https://t.co/LbLbnbMVZl #paper
#Integrated, short-open-load-through (#SOLT) cable/antenna calibration kits https://t.co/LbLbnbMVZl #paper
— Wladek Grabinski (@wladek60) June 16, 2018
from Twitter https://twitter.com/wladek60
June 16, 2018 at 12:15PM
via IFTTT
Jun 14, 2018
#Cryogenic Temperature Characterization of a 28-nm #FDSOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration - IEEE Journals & Magazine https://t.co/ncmOjE3Bqt #paper https://t.co/ncmOjE3Bqt
#Cryogenic Temperature Characterization of a 28-nm #FDSOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration - IEEE Journals & Magazine https://t.co/ncmOjE3Bqt #paper https://t.co/ncmOjE3Bqt
— Wladek Grabinski (@wladek60) June 14, 2018
from Twitter https://twitter.com/wladek60
June 14, 2018 at 03:22AM
via IFTTT
#Cryogenic Temperature Characterization of a 28-nm #FDSOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration - IEEE Journals & Magazine https://t.co/ncmOjE3Bqt #paper
#Cryogenic Temperature Characterization of a 28-nm #FDSOI Dedicated Structure for Advanced CMOS and Quantum Technologies Co-Integration - IEEE Journals & Magazine https://t.co/ncmOjE3Bqt #paper
— Wladek Grabinski (@wladek60) June 14, 2018
from Twitter https://twitter.com/wladek60
June 14, 2018 at 03:21AM
via IFTTT
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