Thursday, 9 June 2011

Freescale's Su calls for improved EDA tools

Freescale's Su calls for improved EDA tools:

As more embedded devices are being connected to the "Internet of things" the design methodologies used in IC designs need to change accordingly for faster chip turnarounds.

Lisa Su, VP and general manager of FreescaleLisa Su, VP and general manager of Freescale"Some 7 billion devices will be connected to the Internet in this era from 2006 to 2020," said Lisa Su, vice president and general manager of Freescale Semiconductor Inc's networking and multimedia group. "And mobile traffic is doubling every year through 2015."

Su delivered the Tuesday (June 7) keynote here at the Design Automation Conference, whose organizers have placed embedded systems and software squarely in the apex of DAC with dedicated exhibit areas on the show floor.

While only 15 exhibitors specifically identified themselves as embedded hardware/software providers out of a total of 200, the technical program was loaded with embedded presentations and Su's keynote was clearly aimed at showing that at least Freescale understands that it is operating in a new space for them, the embedded world.

"The embedded era is defined by standards-based hardware and software, is open source, and aimed numerous markets, including health, safety, energy, transportation, communications, entertainment, automation, and, of course, cloud computing," said Su.

Su quoted statistics that the monthly mobile traffic will increase tenfold from today's 0.6 exabytes to 6.3 exabytes by 2015. "The resultant heterogeneous networks, together with the increasing needs of the รข€˜connected' car, offer many opportunities to semiconductor companies like us," said Su.

The many-core paradigm of the expected SOC technology transition poses a few challenges, according to Su.

Among these are scalability as the number of cores per processor generation will double. Also there will be system tradeoffs to consider between cores versus using hardware acceleration, as well cluster optimization among cores, caches, local vs. global resource sharing. And an increasing amount of high-speed mixed-signal I/O will place strain on expected quality of service metrics.

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