Blog dedicated to the world of compact/SPICE modeling and its Verilog-A standardization. We are discussing the most recent developments and also a bit of history. Obviously, all comments are welcome.
Wednesday, 24 October 2007
A paper on FinFET circuits
In this month's issue of the IEEE Trans. on CAD, there is a very interesting paper from K.Roy et al, who present some interesting techniques to deal with FinFETs to create circuits. Have a look here. The model they present to estimate the current is an alpha-law one, but I should think the idea is nice and could be developed further using more complex (I mean, exact...) models.