Jul 24, 2025
[rsvNumerics] hands-on transistor sizing for analog ICs
Jan 20, 2025
[book] From Code to Chip
- Front Matter pp. i-xv
- Download chapter PDF
- Introduction pp. 1-4
- Theoretical Basics pp. 5-13
- Circuit Capturing pp. 15-36
- PDK—Design Rule Capturing pp. 37-41
- Placement pp. 43-55
- Routing pp. 57-71
- Experimental Results pp. 73-99
- Outlook pp. 101-103
- Back Matter pp. 105-120
Apr 18, 2024
[IEEE SSCS] “PICO” Open-Source Chipathon
The IEEE Solid-State Circuits Society is pleased to announce its fourth open-source integrated circuit (IC) design contest under the umbrella of its PICO Program (Platform for IC Design Outreach). While this contest is open to anyone (no restrictions), we encourage the participation of pre-college students, undergraduates, and geographical regions that are underrepresented within the IC design community.
The goal of this year’s event is to advance the automatic generation and open sharing of analog circuit layout cells to increase our community’s design productivity and to catch up with other fields where sharing and automation is a key enabler of progress (e.g., in machine learning).
Die photo in background courtesy of IBM
Contest Outline
- Interested individuals sign up using this form by May 10, 2024.
- Phase 1 (~June): Through a series of weekly meet-ups and training sessions, the participants learn to create basic one- or two-transistor layout generators using Python and open-source CMOS PDKs. Using Jupyter Notebooks hosted on Google Colab allows anyone with an internet connection to participate - no downloads or installations required! Relevant circuit examples can be found in [1], [2]. We will leverage code modules available with the OpenFASoC [3] environment.
- Phase 2 (~July): Interested participants define larger layout building blocks that they wish to automate (examples: comparator, bandgap, phase interpolator, OTA). Teaming among participants is encouraged to maximize collaboration and learning).
- Phase 3 (~August-September): Participants implement their generators and submit sample layouts and test structures for potential tape-out to an open-source MPW (tentatively SKY130).
- Phase 4 (~October-November): A jury evaluates the created generators/layouts and selects the test structures that will be taped out. The teams work together to assemble a shared database with all the designs and to complete the tapeout. Ideally, this phase will involve automated verification through CACE [4] or a similar tool.
- Phase 5 (TBD): The designs will be tested using lab measurements by a subset of participants and SSCS volunteers with access to lab facilities. Some of the test setups may be available for remote characterization. The obtained measurement data will be added to the repositories containing the layout generators.
References
[1] H. Pretl, “Fifty Nifty Variations of Two-Transistor Circuits,” MOS-AK Workshop Spring 2022, URL: https://www.mos-ak.org/spring_2022/presentations/Pretl_Spring_MOS-AK_2022.pdf.[2] H. Pretl and M. Eberlein, "Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs," in IEEE Solid-State Circuits Magazine, vol. 13, no. 3, pp. 38-46, Summer 2021, URL: https://ieeexplore.ieee.org/document/9523464.
[3] OpenFASoC: Fully Open-Source Autonomous SoC Synthesis using Customizable Cell-Based Synthesizable Analog Circuits, https://github.com/idea-fasoc/OpenFASOC/.
[4] Circuit Automatic Characterization Engine, URL: https://github.com/efabless/cace.
Apr 15, 2024
[course] MEAD @ EPFL
MONDAY, June 17 | ||
8:30 am-12:00 pm | MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design | Christian Enz |
1:30-5:00 pm | Design of Low-Power Analog Circuits using the Inversion Coefficient | Christian Enz |
TUESDAY, June 18 | ||
8:30 am-12:00 pm | Noise Performance of Elementary Circuit Blocks | Boris Murmann |
1:30-5:00 pm | Opamp Topologies and Design Fundamentals | Boris Murmann |
WEDNESDAY, June 19 | ||
8:30-10:00 am | Low-Power High Efficiency OpAmp Design | Klaas Bult |
10:30 am-12:00 pm | Low-Power High Efficiency Residue Amplifiers | Klaas Bult |
1:30-3:00 pm | Analog Design Methodology and Practical Techniques for Frequency Compensation | Vadim Ivanov |
3:30-5:00 pm | Energy Efficient Voltage References, Biasing in Analog Systems and Current Sources | Vadim Ivanov |
THURSDAY, June 20 | ||
8:30-10:00 am | Power Dissipation in ADC Buidling Blocks | Klaas Bult |
10:30 am-12:00 pm | Power Dissipation in ADCs | Klaas Bult |
1:30-5:00 pm | Micropower ADCs | Kofi Makinwa |
FRIDAY, June 21 | ||
8:30 am-12:00 pm | Energy Efficient Sensor Interfaces | Taekwang Jang |
1:30-5:00 pm | Low-Power Frequency Reference Circuits | Taekwang Jang |
1:30-5:00 pm | Power Management With Nanoampere Consumption and Efficient Energy Harvesting | Vadim Ivanov |
Mar 18, 2024
[paper] Symmetric BSIM-SOI
Oct 31, 2023
[paper] Analog System Synthesis for Reconfigurable Computing
* Electrical and Computer Engineering (ECE), Georgia Institute of Technology (USA)
May 17, 2023
[chapter] Systematic Design of Analog CMOS Circuits with Lookup Tables
Oct 20, 2021
[paper] CMOS floating-gate device for quantum control hardware
2 Istituto di Fotonica e Nanotecnologie, Consiglio Nazionale delle Ricerche (I)
Oct 12, 2020
[chapter] Low-Voltage Analog IC Design
Aug 25, 2020
Analog IC Designer's Handbook
Aug 28, 2017
[paper] Nanoscale MOSFET Modeling
Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits
Feb 17, 2017
[call for papers] 2017 IEEE S3S Conference

Tuesday, Oct.17: Monolithic 3D Half-day Tutorial
Scope: We welcome papers in the following areas: | |
Silicon On Insulator (SOI) | |
• Advanced Materials,
Substrate and Processes • Device Physics, Characterization and Modeling • Device/Circuit Integration • SOI Design, Circuits and Applications |
• Non-Digital Devices and
Applications (RF, HV, Photonics, NEMS, MEMS, Analog...) • New SOI Structures, Circuits and Applications |
Low-Voltage Microelectronics | |
• Space-Based and Unattended
Remote Sensors • Biomedical Devices • Low-Voltage Handheld/wireless systems • Ultra-Low-Power Digital Computation • Analog and RF Technologies |
• Low Voltage Memory
Technologies • Energy Harvesting Techniques • Asynchronous Circuits • Novel Device and Fabrication Technology |
3D Integration | |
• Low Thermal Budget
Processing • Fabrication Techniques and Bonding Methods • Design and Test Methodologies • Processes for Multi Wafer Stacking • 3D IC EDA and Design Technology |
• Heterogeneous Structures • 3D Manufacturing and Logistics • Reliability of 3D Circuits • Fault Tolerant 3D Designs |
Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.
Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392
Feb 7, 2017
[paper] Impact of technology scaling on analog and RF performance of SOI–TFET
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4
Abstract
Citations
[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al 2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al 2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al 2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al 2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al 2015 447
Mar 5, 2012
NDES 2012 July 11 – 13, 2012, Wolfenbüttel, Germany
- Theory, analysis, modelling, implementations and applications of nonlinear circuits and systems in science, technology and biology
- Nonlinear network analysis
- Neural networks, neurodynamics, robots
- Nonlinear signal processing: Time-series analysis, communication, coding
- Nonlinear devices: Sensors, lasers
- Bifurcation and chaos, control and synchronisation
- Geodynamics
Ruedi Stoop (Conference Co-Chair, Organizing Committee)
Jan 24, 2010
ISSCC 2010 Preview: Assessing '05 predictions
Apr 17, 2009
CMOS vs. Bipolar Operational Amplifiers: Which is best for my application?
- Power Consumption
- Voltage Offset
- Noise Performance
Apr 15, 2009
7th IEEE EWDTS SYMPOSIUM
Symposium Deadlines:
- Submission deadline: May 30th, 2009
- Notification of acceptance: August 1st, 2009
Apr 8, 2009
April 14, 2009: ESSDERC/ESSCIRC submission deadlines
Visit the conference web site: http://www.essderc2009.org
Mar 30, 2009
after Analogschaltungen'09 in Hannover
- Novel CMOS/BiCMOS circuit architectures for the GHz range applications
- Models of semiconductor devices for analog/RF (GHz range) applications
- Influences of the system design and optimization on the components in the analog circuit applications
- Classical and quantum mechanical effects in analog/RF nano-silicon circuits at GHz frequencies
- Prof. Dr. -Ing. Wolfgang Mathis, Leibniz Universität Hannover, Institut für Theoretische Elektrotechnik; Appelstr. 9A, 30167 Hannover
- Prof. Dr.rer. nat. Doris Schmitt- Landsiedel, TU München; Lehrstuhl für Technische Elektronik
- Prof. Dr. -Ing. Heinrich Klar, TU Berlin; Institut für Technische Informatik und Mikroelektronik
- Prof. Dr.-Ing. Y. Manoli, Universität Freiburg; IMTEK