Nov 26, 2017
[paper] Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s
Assessment of Germanane Field-Effect Transistors for CMOS Technology https://t.co/9nONoZjS12 #paper
Assessment of Germanane Field-Effect Transistors for CMOS Technology https://t.co/9nONoZjS12 #paper
— Wladek Grabinski (@wladek60) November 25, 2017
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November 26, 2017 at 12:25AM
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Nov 25, 2017
#Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors https://t.co/Ql0DQWQ5hf
#Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors https://t.co/Ql0DQWQ5hf
— Wladek Grabinski (@wladek60) November 25, 2017
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November 25, 2017 at 06:09PM
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Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond https://t.co/sGwqx6xw7E #paper
Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond https://t.co/sGwqx6xw7E #paper
— Wladek Grabinski (@wladek60) November 25, 2017
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November 25, 2017 at 04:31PM
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TCAD Mobility #Model of III-V Short-Channel Double-Gate FETs Including Ballistic Corrections https://t.co/xAcLMzh4S9
TCAD Mobility #Model of III-V Short-Channel Double-Gate FETs Including Ballistic Corrections https://t.co/xAcLMzh4S9
— Wladek Grabinski (@wladek60) November 25, 2017
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November 25, 2017 at 06:04PM
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Nov 24, 2017
A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its... https://t.co/zg9x86qUaH
A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its... https://t.co/zg9x86qUaH
— Wladek Grabinski (@wladek60) November 24, 2017
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November 24, 2017 at 09:39PM
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A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its Circuit Validation - IEEE Journals & Magazine https://t.co/NgDkKN8gxr
A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its Circuit Validation - IEEE Journals & Magazine https://t.co/NgDkKN8gxr
— Wladek Grabinski (@wladek60) November 24, 2017
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November 24, 2017 at 09:39PM
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Nov 22, 2017
Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction https://t.co/6djtGE7OZV #paper https://t.co/RYLH3fSGhg
Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction https://t.co/6djtGE7OZV #paper http://pic.twitter.com/RYLH3fSGhg
— Wladek Grabinski (@wladek60) November 21, 2017
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November 21, 2017 at 11:54PM
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A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation https://t.co/R0t2mdhbMF #paper
A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation https://t.co/R0t2mdhbMF #paper
— Wladek Grabinski (@wladek60) November 21, 2017
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November 21, 2017 at 11:18PM
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Nov 21, 2017
[mos-ak] [Final Program] 10th International MOS-AK Workshop in the Silicon Valley
Scheduled,10th subsequent MOS-AK modeling workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:
Venue:
Online Workshop Registration is still openCadence Design Systems2655 Seely AveSan Jose, CA 95134
Postworkshop Publications:
in a special issue of the International Journal of High Speed Electronics and Systems
Extended MOS-AK Committee
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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus... https://t.co/vekyZr5RmC
Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus... https://t.co/vekyZr5RmC
— Wladek Grabinski (@wladek60) November 21, 2017
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November 21, 2017 at 04:49PM
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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus geometrical Si nanowire characteristics https://t.co/OnvqDTh6l2
Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus geometrical Si nanowire characteristics https://t.co/OnvqDTh6l2
— Wladek Grabinski (@wladek60) November 21, 2017
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November 21, 2017 at 04:48PM
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Nov 16, 2017
#Banks are increasingly turning to #opensource projects. Here’s why. https://t.co/FHoU5O7jdZ
#Banks are increasingly turning to #opensource projects. Here’s why. https://t.co/FHoU5O7jdZ
— Wladek Grabinski (@wladek60) November 16, 2017
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November 16, 2017 at 12:54PM
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Innovations in Electronics and Communication Engineering
Nov 14, 2017
The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM
The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM
— Wladek Grabinski (@wladek60) November 14, 2017
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November 14, 2017 at 10:45PM
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3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X https://t.co/V68oi64jF3
3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X http://pic.twitter.com/V68oi64jF3
— Wladek Grabinski (@wladek60) November 14, 2017
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November 14, 2017 at 10:38AM
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7th All-Russian Workshop on CAD of IC Design
08:45 - 09:15 | Registration (University entrance) |
09:30 - 13:00 | Conference hall 3rd floor of the main lecture building |
- Synthesis in Genus (28nm technology) | |
- Introduction to Joules | |
- Innovus 17.1 Topical Introduction | |
13:00 - 14:00 | Lunch break |
14:00 - 18:15 | Conference hall 3rd floor of the main lecture building |
- Introduction to Stylus | |
- Physical verification with the help of PVS | |
- A new generation of verification software - Xcelium and Indago | |
- The history and future of megatrends in EDA |
9:00 - 18:00 | Laboratory V-315 of the Department of Electronics (Practical classes) |
- Behavioral modeling | |
- Logical synthesis | |
- Simulation of a Verilog modules with element delays | |
- Physical design of the digital modules | |
- Verification of the digital modules |
10:00 - 12:00 | Laboratory V-315 of the Department of Electronics |
- Working discussions, summarizing |
Contact Event Secretary: E. Atkin
+7 495 7885699 ext. 9155
+7 499 3242597
Nov 11, 2017
#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2
#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2
— Wladek Grabinski (@wladek60) November 11, 2017
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November 11, 2017 at 07:15PM
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#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr
#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr
— Wladek Grabinski (@wladek60) November 11, 2017
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November 11, 2017 at 09:39AM
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Nov 7, 2017
ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling https://t.co/c5INhqX0yD
ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling http://pic.twitter.com/c5INhqX0yD
— Wladek Grabinski (@wladek60) November 7, 2017
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November 07, 2017 at 08:36PM
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Nov 6, 2017
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper
— Wladek Grabinski (@wladek60) November 6, 2017
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November 06, 2017 at 08:26PM
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Nov 3, 2017
[paper] Validation of MOSFET Model Source–Drain Symmetry
doi: 10.1109/TED.2006.881005
Nov 2, 2017
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:43AM
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Analytical #modeling is both science and art https://t.co/DBdMqRJqkU https://t.co/G45cufzKTb
Analytical #modeling is both science and art https://t.co/DBdMqRJqkU http://pic.twitter.com/G45cufzKTb
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:07AM
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#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27
— Wladek Grabinski (@wladek60) November 2, 2017
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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R
— Wladek Grabinski (@wladek60) November 2, 2017
from Twitter https://twitter.com/wladek60
November 02, 2017 at 10:04AM
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