[C4P] WOSET 2024

Call for Papers

Workshop on Open Source EDA Technologies (WOSET)

https://woset-workshop.github.io/

Virtual! No registration fee! 

Submission Due Date: Sept 23 2024 

The WOSET workshop aims to galvanize the open-source EDA movement. The workshop will (virtually) bring together EDA researchers who are committed to open-source principles to share their experiences and coordinate efforts towards developing a reliable, fully open-source EDA flow. The workshop will feature presentations that overview existing or under-development open-source tools, designs and technology libraries. Break-out rooms will be utilized for discussion of works-in-progress. The workshop will feature a panel on the present status and future challenges in open-source EDA, and how to coordinate efforts and ensure quality and interoperability across open-source tools.

Topics of interest include, but are not limited to:

• Overview of an existing or under-development open-source EDA tool.
• Overview of support infrastructure (e.g. EDA databases and design benchmarks).
• Open-source cloud-based EDA tools
• Open-source hardware designs
• Position statements (e.g. critical gaps, blockers/obstacles)

Submission Information:

• All submissions must include links to open-source repositories with
•   all source code and an open-source license (BSD, GPL, Apache, etc.)
• Please reference your open-source repository!
• Review is single blind (anonymous reviewers).
• Videos will be put on the WOSET site if accepted.
• Virtual presentation for regular papers (in addition to archival video)
• Regular Paper Submissions (4 pages + 1 page references + 15 min video + virtual presentation)
• Work in Progress Submissions (2 page abstract + 1 page references + 10 min video + virtual zoom room)
• Submission site: https://openreview.net/group?id=WOSET-Workshop.github.io/2024

Important dates:

• Sept 23 2024 (end of day, anywhere in the world): submission due date.
• Oct 18 2024: notification date.
• Nov 8 2024: video due (if accepted)
• Nov 18 2024: workshop

Co-Chairs:

• Matthew Guthaus, UC Santa Cruz 
• Jose Renau, UC Santa Cruz

Program Chair:

• Dustin Richmond, UC Santa Cruz

Proceedings Chair:

• Dan Petrisko, University of Washington

Zoom Chair:

• Seeking volunteers to help run the virtual meeting

Program Committee:

• Jonathan Balkind, UC Santa Barbara
• Tim Edwards, efabless
• Steve Hoover, Redwood EDA
• Lucas Klemmer, JKU Linz
• Dirk Koch, University of Manchester
• Christian Krieg, TU Wien
• Rajit Manohar, Yale University
• Guillem Lopez Paradis, Barcelona Supercomputing Center
• Frans Skarman, Linköping University
• Matt Venn, YosysHQ, TinyTapeout

[paper] anybody can design and build a chip

Krzysztof Herman, Norbert Herfurth, Tim Henkes, Sergei Andreev, Rene Scholz, Markus Müller, Mario Krattenmacher, Harald Pretl, and Wladyslaw Grabinski

On the Versatility of the IHP BiCMOS Open Source and Manufacturable PDK: 

A step towards the future where anybody can design and build a chip

IEEE Solid-State Circuits Magazine, vol. 16, no. 2, pp. 30-38, Spring 2024

DOI: 10.1109/MSSC.2024.3372907

Abstract: In this article, we introduce the first European open source process design kit (PDK), namely IHP-Open130-G2. We provide a concise history of the PDK itself and offer a brief comparison with some alternative open source PDKs, such as SKY130 and GF180MCU. The article also includes a process description and details on deliverables, offering insights into available devices, models, supported open source tools, and workflows. As the IHP-Open130-G2 is currently under development, we present key points outlining future activities. This aims to inform and attract users to join the open source silicon community. The concluding section of the article compares measurement results for active devices with compact model results. The article concludes with a cryptographic Internet protocol (IP) core based on IHP-Open130-G2 as an exemplary use case.

FIG: Silicon Proven Application: The final layout of the HEP custom cryptographic IP core.

[REF] “130nm BiCMOS open source PDK, dedicated for analog, mixed signal and RF design.” GitHub. Online: https://github.com/IHP-GmbH/IHP-Open-PDK

[Latch-Up] IHP Open Source PDK

IHP Open Source PDK:

Announcement, Setup, Current State and Experiences, and look ahead

Frank Vater, IHP Frankfurt (Oder), Germany

Latch-Up 2024 video

Abstract: Main focus of this talk is the SG13G2 Open Source PDK for IHP 130nm BiCMOS technology. The current state of our activities will be given for the analogue as well as for the digital PDK including design flow with open source tools. Some more details on first experiences for schematic driven design, simulation, layout, DRC and LVS will be pointed out. Furthermore, already known challenges analogue and digital design flow and open issues on open source tool chain will be addressed. The talk will be closed with a road map for future work.

Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.

Produced by NDV: @nextdayvideo
OpenHardware Sat Apr 20 16:20:00 2024 at b45r230

[Kick-off] Chipdesign Germany

Chipdesign Germany

Das Netzwerk für Chipdesign in Deutschland

https://www.chipdesign-germany.de/

OnLine Registrierung: https://eveeno.com/auftaktchipdesigngermany

Juni 6. Donnerstag

13:00 Ankunft & Registrierung
14:00 Eröffnung
14:00 Begrüßung

Holger Blume; Leibniz Universität Hannover & edacentrum e.V.

14:15 Grußworte

Apollonia Pane Bundesministerium für Bildung und Forschung 

14:30 Vorstellung Chipdesign Germany

Holger Blume; Leibniz Universität Hannover & edacentrum e.V.
Norbert Wehn; Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau

14:45 Keynote-Session I

14:45 Open-Source EDA and Innovation Leadership
Andrew B. Kahng; University of California San Diego, US

15:45 Kaffeepause
16:30 Keynote-Session II

16:30 Open Source Chip Design: Europas Weg zur Wettbewerbsfähigkeit in einer geteilten Tech-Welt?

Jan-Peter Kleinhans; Stiftung Neue Verantwortung

17:30 Mikroelektronik in digitalen Hörhilfen: Chips, die hören helfen

Joachim Thiemann; Advanced Bionic

18:30 Networking-Veranstaltung mit Poster- & Demo-Session

Juni 7. Freitag

08:30 Eröffnung
08:30 Begrüßung

Holger Blume; Leibniz Universität Hannover & edacentrum e.V

08:45 Keynote-Session III
08:45 Neue Fertigungstechnik für die Chipverarbeitung

Lutz Rissing; Dr. Johannes Heidenhain GmbH

09:45 Kaffeepause
10:30 DE:Sign Präsentationen

BMBF-Förderlinie "Design-Instrumente für souveräne Chipentwicklung mit Open-Source (DE:Sign)"

10:30 DI-OCRCpro

Daniel Krupka; Gesellschaft für Informatik e.V.

10:45 DI-DEMICO

Frank Ellinger; Technische Universität Dresden

11:00 DI-DERAMSys

Matthias Jung; Julius-Maximilian-Universität Würzburg

11:15 DI-OWAS

Dirk Koch; Ruprecht-Karls-Universität Heidelberg

11:30 DI-PASSIONATE

Robert Weigel; Friedrich-Alexander Universität Erlangen-Nürnberg

11:45 Interaktive Poster-Session
13:30 Verabschiedung

Adresse: Königlicher Pferdestall - Leibniz Universität Hannover; Appelstr. 7, 30167 Hannover
OnLine Registrierung: https://eveeno.com/auftaktchipdesigngermany

[FOSSEE] Better Education

FOSSEE (Free/Libre and Open Source Software for Education) project promotes the use of free open source software (FOSS) tools in academia and research. The FOSSEE project is part of the National Mission on Education through Information and Communication Technology (ICT), Ministry of Education (MoE), Government of India. 

Below is the list of projects which are promoted by FOSSEE.

• Scilab 
  free/libre and open source software for numerical computation developed by Scilab Enterprises, France. Scilab also includes Xcos which is an open source alternative to Simulink.
• Python 
  general-purpose, high-level, remarkably powerful dynamic programming language that is used in a wide variety of application domains. It supports multiple programming paradigms.
• eSim 
  (formerly known as Oscad/FreeEDA) is an EDA tool for circuit design, simulation, analysis and PCB design. It is developed by the FOSSEE team at IIT Bombay 
• Osdag 
  free/libre and open-source software which allows the user to design steel structures using a graphical user interface. The GUI also provides 3D visualization of the designed component and images
• DWSIM 
  free/libre and open source CAPE-OPEN compliant chemical process simulator. Helps understand the behavior of Chemical Systems by using rigorous thermodynamic and unit operations models.
• OpenFOAM 
  free/libre and open source CFD toolbox useful to solve anything from complex fluid flows involving chemical reactions, turbulence and heat transfer, to solid dynamics and electromagnetics.
• OpenModelica 
  free/libre and open source environment based on the Modelica modelling language for modelling, simulating, optimising and analysing complex dynamic systems.
• OpenPLC 
  free/libre and open source Programmable Logic Controller creating opportunities for people to study its concepts, explore new technologies and share the resources.
• FLOSS-Arduino
  control of Arduino using Free/Libre Open-Source Software. The interface helps the user to perform embedded systems experiments on the Arduino Uno board.
• SBHS
  (Single Board Heater System) is a lab-in-a-box setup useful for teaching and learning control systems.
• R 
  programing language and environment for statistical computing and graphics.
• QGIS
  (Quantum GIS) is a free and open-source desktop Geographic Information System (GIS) application.
• FOCAL 
  an initiative by FOSSEE to promote Open Source Software in computer graphics.
• SOUL
  (Science OpensoUrce Software for Teaching Learning) is a collection of ICT software that can be used as teaching/learning tools by the community of educators and the learners to teach/ learn the basic as well as the advanced concepts in science subjects

[paper] Open-source design of integrated circuits

Patrick Fath, Manuel Moser, Georg Zachl. Harald Pret

Open-source design of integrated circuits

Elektrotech. Inftech. (2024)

DOI: 10.1007/s00502-023-01195-5

* Institute for Integrated Circuits, Johannes Kepler University Linz, Austria

Abstract: This paper presents the design of a self-clocked 12-bit non-binary fully differential SAR-ADC using the SKY130 open-source PDK. The entire mixed-signal circuit design and layout were created with free and open-source software. The ADC reaches a sample rate of up to 1.44MS/s at 1.8V supply while consuming 703μW of power on a small 0.175mm area. A configurable decimation filter can increase the ADC resolution up to 16 bits while using an oversampling factor of 256. A 9‑bit thermometer-coded and 3‑bit binary-coded DAC matrix using a 448 aF waffle-capacitor results in a total capacitance of 1.83pF per input. Realizations of configurable analog functions using the form factor of SKY130 high-density standard cells allow the parametrization of an analog circuit in a hardware description language and hardening of the macro in an intentionally digital workflow.

FIG: Block diagram of the proposed open-source design flow,

including the essential tools and used/generated files

Acknowledgements: The authors thank Johannes Kepler University for funding the open-access publication, Google and SkyWater Technologies for igniting this recent wave of open-source IC design, and the large crowd of enthusiasts spending their time on developing and maintaining an extensive array of exciting open-source EDA projects. Open access funding provided by Johannes Kepler University, Linz.

ISHI-kai January 2024 event

2024年1月イベント「オープンソースPDK団体」勉強会国内外のオ
ープンソースPDKやEDAの状況について、キーマンに語っていただきます

With the recent rise in the semiconductor industry, the movement of open source PDK and EDA in Japan and overseas has become active. Therefore, in this study session, key people will talk about the status of open source PDK and EDA in Japan and overseas.

Schedule

Friday, January 26, 2024, 18:00-21:00 (Reception: 18:30)

Venue (onsite)

Google Shibuya Office
3-21-3 Shibuya, Shibuya-ku, Tokyo
Shibuya Stream Google reception meeting

Online Broadcast: 

Google Meet: https://meet.google.com/ksa-tjaw-ges

Participation Fee

free

Timetable

Time	Speaker	Title	Lecture Outline
Until 18:30	ISHI-kai	reception	The entrance to the facility closes at this time, so if you are participating locally, please come by this time as much as possible.
18:00 ～ 18:30	ISHI-kai	Chat time	-
18:30 ~ 19:15 (Lecture: 30min, Q&A: 15min)	Takeshi Hamamoto Minimal Fab Propulsion Organization Device Engineer	minimal Fab open PDK	1) What is a minimal fab 2) openPDK 3) Design Contest at Semicon 2023
19:15 ~ 20:00 (Lecture: 30min., Q&A: 15min.)	Junichi Okamura IEEE Senior Member	OpenPDK and the World	-
20:00 ~ 20:45 (Lecture: 30min., Q&A: 15min.)	@noritsuna	About the upcoming open source PDK shuttle	(To be released at a later date)
21:00	ISHI-kai	closing

What is ISHI-kai?

The association was named ISHI-kai (Inter-linked Society on Homemade IC Kai). The name was conceived from the Society Community (Association) that handles open (democratized) ISHI = stone = Silicon = semiconductors (ASIC/LSI/IC) and connects various fields.

OpenMPW (Open Multi Project Wafer), which appeared as a forerunner, is a shuttle program created by Google investing in Efabless, and includes the tools necessary for making semiconductors (ASIC/LSI/IC) (EDA/PDK) to ISHI manufacturing in IC fabs). This is exactly the "openness of semiconductors (ASIC/LSI/IC) and EDA/PDK" of the open source movement (democratization of software) that started with GNU!

Therefore, this association was established as a user society community (association) that focuses not only on experts in semiconductors (ASIC/LSI/IC) in the past, but also on those who see the potential of the open source movement of semiconductors (ASIC/LSI/IC) in the future and those who want to create new semiconductors (ASIC/LSI/IC).

We/ISHI-kai will continue to work toward a world where semiconductors (ASIC/LSI/IC) and EDA/PDK can be used by everyone, just as OSs, compilers, libraries, apps, electronic boards, 3D CAD and 3D printers that we/ISHI-kaire only available to experts can now be used by everyone as open source software, open hardware, open modeling, etc.

As for the future activity plan, we/ISHI-kai have a policy of revolutionizing the semiconductor (ASIC/LSI/IC) field by involving people from other fields, and we/ISHI-kai will hold events such as hands-on seminars for ultra-beginners for other fields and in-depth study sessions for experts, form a team to challenge the OpenMPW shuttle and Chipathon from around the world, and Maker we/ISHI-kai would like to participate in events such as Faire, so thank you.

Precautions

As events move online, we/ISHI-kai ask participants to act in accordance with the spirit of the Code of Conduct. If you have any problems, please contact the organizer. If it is judged that there is no improvement in the request even if there is no abuse such as vandalism or malicious intent, we/ISHI-kai may respond on a case-by-case basis. 

https://www.contributor-covenant.org/ja/version/2/0/code_of_conduct/

Acknowledgements

Thanks to the kindness of Google for providing a real/onsite venue.

[webinar] Open Source Silicon Landscape

Unveiling the Open Source Silicon Landscape: 

a cutting-edge approach for the European semiconductor industry

5 December 2023

Who should attend and why:

• Policymakers at the regional, national, and European level who want to strengthen their respective semiconductor ecosystem while collaborating and contributing to the Union’s industry as a whole
• Research and academia representatives who are interested in deepening their knowledge or discovering the potential of the Open Source Silicon landscape
• SMEs in the semiconductor industry who aim to expand and innovate their business by using a cutting-edge approach
• Start-ups that are eager to elevate their business to the next level by embracing vanguard strategies
• Citizen scientists and the general public who would like to have a better understanding of the new horizons in the semiconductor landscape
• Experts active in industrial development who are interested in integrating potential new approaches

Registration:

The event is free of charge, but registration is mandatory. Registrants will receive the link to access the event by email.

Agenda:

11:00 - 11:05	Welcome
11:05 - 11:10	Introducing Open Source Silicon
11:10 - 11:20	BACKGROUND Open source silicon between software and hardware Background
11:20 - 11:40	POLICY BRIEF PRESENTATION Open source silicon’s position in the semiconductor value chain
11:40 - 12:35	PANEL Key opportunities and threats relevant to open source silicon strategies
12:35 - 12:45	Q&A and conclusions

GoIT project at Open Source Experience Event

Laboratoire d'Informatique de Paris 6 (LIP6) Sorbonne and CNRS will attend Open Source Experience event on 6-7 December in Paris to present GoIT project

Come and join the European open source community meeting!!

[ read more... ]

3rd MFEM Community Workshop, October 26, 2023

MFEM is a free, open source, lightweight, scalable C++ library for finite element methods.

Features

• Arbitrary high-order finite element meshes and spaces.
• Wide variety of finite element discretization approaches.
• Conforming and nonconforming adaptive mesh refinement.
• Scalable from laptops to GPU-accelerated supercomputers.
• ... and many more.
• See MFEM Gallery, Publications, Videos and News pages.

MFEM is used in many projects, including BLAST, Cardioid, Palace, VisIt, RF-SciDAC, FASTMath, xSDK, and CEED in the Exascale Computing Project.

Annual workshop 

MFEM host an annual workshop and FEM@LLNL seminar series. The MFEM team has  announced the 3rd MFEM Community Workshop, which will take place on October 26, 2023, virtually, using Zoom for videoconferencing. The goal of the workshop is to foster collaboration among all MFEM users and developers, share the latest MFEM features with the broader community, deepen application engagements, and solicit feedback to guide future development directions for the project.

Registration
If you plan to attend, please register no later than October 19th. There is no registration fee. Zoom details will be distributed to participants prior to the event date. For questions, please contact the meeting organizers at mfem@llnl.gov.

[video] Interviews from FSiC, Paris, 2023

Interviews from the Free Silicon Conference, Paris, 2023

The 2023 Free Silicon Conference (FSiC) took place in Paris (Sorbonne Université, 4 Place Jussieu, Paris) on July 10 - 12 2023 (Monday to Wednesday). The conference brought together experts and enthusiasts who want to build a complete Free and Open Source CAD ecosystem for designing analog and digital integrated circuits. The conference covered the full spectrum of the design process, from system architecture, to layout and verification.

Interviews with selected Free Silicon Conference Participation by Matt Venn are available online:

00:00 FSiC 2023 Intro, Matt Venn

00:23 Luca Alloatti, FSiC Organizing Committee

01:59 Thomas Benz, ETH Zurich

06:05 Jørgen Kragh Jakobsen, IC Works - Open Source Chip Design

08:57 Thomas Parry, SPHERICAL

11:05 Rene Scholz, IHP Microelectronics

14:06 Dan Fritchman, UC Berkeley
18:41 Harald Pretl, Johannes Kepler University Linz

All the conference proceedings (slide presentations and prerecorded talks) are also available at the FSiC website.

[Workshop] Open Source PDKs and EDA

 Workshop 1: Open Source PDKs and EDAs, 

Community Experiences toward Democratization of Chip Design

RIHGA Royal Hotel Kyoto, Horikawa Shiokoji, Shimogyo ku, Kyoto 600 8237, Japan.

Date & Time: 5:30pm.-7:15pm on June 11 (Sun), 2023

Since its launch in 2020, the Open MPW shuttle program has received over 500 project submissions spanning 9 shuttles. This workshop will explore various topics related to designers' experiences, including measured results, foundry perspectives, and governmental expectations.

Organizers: 

• Makoto Ikeda (The University of Tokyo)
• Mehdi Saligane (University of Michigan)

Program:

1. Design experience: “The Journey of Two Novice LSI Enthusiasts: Tape-Out of CPU+RAM in Just One Month”, Kazuhide Uchiyama, University of Electro-Communications and Yuki Azuma, University of Tsukuba
2. From Zero to 1000 Open Source Custom Designs in Two Years, Mohamed Kassem, Co-founder and CTO, Efabless
3. The SKY130 Open Source PDK: Building an Open Source Innovation Ecosystem, Steve Kosier, Skywater technology
4. Open Source Chip Design on GF180MCU – A foundry perspective, Karthik Chandrasekaran, Global Foundries
5. Japan Foundries' Perspectives on Silicon design democratization, Shiro Hara, Minimal Fab & AIST
6. Google's perspective on Open source PDKs, Open source EDA tools, and OpenMPW shuttle program, Johan Euphrosine and Tim Ansell, Google
7. The Nanofabrication Accelerator Project, Matthew Daniels, NIST
8. Japanese government perspective on Silicon design democratization, Yohei Ogino, The Ministry of Economy, Trade and Industry METI

VLSI Symposium Workshop1 "Open Source PDKs and EDA" Audience

[analog-wg] Video of March 21 AWG Meeting

The Analog Workgroup (AWG) was formed by the CHIPS Alliance TSC to explore collaborations in open source Analog/Mixed-Signal design and verification. It focuses on sharing best practices, ideas, tooling (analog automation), and other challenge areas in the design space. The workgroup is composed of both industry and university members.

The AWG Video Meeting on March 21, 2023 included two presentations:

• Ken Kundert "Why Fund OpenVAF"
• Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"

Please note the following line of topics for the Analog Workgroup

• 4th April: Update from Tim Edwards: Magic and PEX extraction
• 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development 
• 2nd May (tentative): Update from C. Enz,EPFL:  test structures measurements

[open position] IHP Research Associate for Open PDK Development

Research Associate for Open PDK Development (m/f/d)

Developer for Open Source Process Design Kits

for SiGe-BiCMOS Technology

Job-ID: 7011/23 | Department: Technology | Salary: as per tariff TV-L | Working time: 40h/week (part-time work option) | Limitation: initially 2 years with option of extension for three more years | Entry Date: as soon as possible

IHP is an institute of the Leibniz Association and conducts research and development of silicon-based systems and ultra-high-frequency circuits and technologies, including new materials. It develops innovative solutions for application areas such as wireless and broadband communication, security, medical technology, industry 4.0, automotive industry, and aerospace. IHP employs approximately 350 people. It operates a pilot line for technological developments and the preparation of high-speed circuits with 0.13/0.25 µm-SiGe-BiCMOS technologies, located in a 1500 m² cleanroom that meets the highest industrial nanotechnology requirements.

The position:

As a member of the group Research & Prototyping Service, you will develop Process Design Kit for IHP’s BiCMOS technologies and new future technology modules with special focus on open source PDK development. Your detailed tasks will include programming of pCells and their integration into our verification process. Devices descriptions, user guides and test cases are important aspects of your work, too. Finally, managing our PDK repositories on Github with external contributions and adaption of existing tools like OpenRAM is part of the work. Implementation of new devices and investigations of new design tools and flows will give this position room for interesting development opportunities.

Your profile:

You hold a Master's degree in computer science with background in semiconductors, physics or electrical engineering. Knowledge in semiconductor devices and programming are of advantage. Your specialized knowledge preferably covers ASIC design environment like Cadence Virtuoso, Mentor/Siemens Tanner or KeySight ADS, OpenROAD/OpenLane, Linux and scripting languages (e.g. Python, Perl or TCL). You are well organized and always keep the overview even with many parallel projects. Thanks to your skillful communication, you are a binding and reliable contact person for our partners. You are also a strong team player, and you confidently handle the German and English language. You are also a strong team player. We are looking for a team member, who is able to structure his or her own work and to bring a well-organized and systematic way of working into the cooperation with creative minds. You are an ideal match for this position, when you have experimental, analytical and problem-solving skills, very strong communicative skills and the ability to quickly learn how to operate the latest technical equipment including various software. It is necessary that you confidently handle the English language. Knowledge of the German language is welcome. The consolidating of German language skills is expected and highly encouraged, for example in in-house language courses and intensive courses.

Your application:
Have we sparked your interest? Then we look forward to receiving your application via our online application form. For further information regarding the position, please contact Dr. René Scholz

[paper] OpenSpike: An OpenRAM SNN Accelerator

Farhad Modaresi¹, Matthew Guthaus², and Jason K. Eshraghian³
OpenSpike: An OpenRAM SNN Accelerator
arXiv:2302.01015v1 [cs.AR] 2 Feb 2023

1) Dept. of Electrical Engineering Allameh Mohaddes Nouri University Nur, Mazandaran, Iran
2) Dept. of Computer Science and Engineering, UC Santa Cruz Santa Cruz, CA, United States
3) Dept. of Electrical and Computer Engineering, UC Santa Cruz Santa Cruz, CA, United States

Abstract: This paper presents a spiking neural network (SNN) accelerator made using fully open-source EDA tools, process design kit (PDK), and memory macros synthesized using Open- RAM. The chip is taped out in the 130 nm SkyWater process and integrates over 1 million synaptic weights, and offers a reprogrammable architecture. It operates at a clock speed of 40 MHz, a supply of 1.8 V, uses a PicoRV32 core for control, and occupies an area of 33.3 mm2. The throughput of the accelerator is 48,262 images per second with a wallclock time of 20.72 μs, at 56.8 GOPS/W. The spiking neurons use hysteresis to provide an adaptive threshold (i.e., a Schmitt trigger) which can reduce state instability. This results in high performing SNNs across a range of benchmarks that remain competitive with state-of-the-art, full precision SNNs.

The design is open sourced and available online: https://github.com/sfmth/OpenSpike

Fig: OpenSpike core - system architecture and data flow

 

 

[OpenVAF] Next-Generation Verilog-A Compiler

OpenVAF is a Next-Generation Verilog-A compiler

that empowers the open source silicon revolution

Roadmap: OpenVAF is still in development and there many goals we aim to achieve in the longterm:

• Noise analysis (planned for 2023)
• Reaching full compliance with the Verilog-A standard
• Behavioral modelling features
• Support for features that allow defining full circuits/full PDKs in Verilog-A
• OSDI integration in Xyce
• Improved documentation
• A detailed paper about the technical innovations in OpenVAF and attendance at international conferences

We, OpenVAF Developers, are always looking for cooperation partners, please do not hesitate to contact SemiMod GmbH.

Circuit simulators play a critical role in the design of electrical circuits. Accurate simulations enable circuit designers to validate circuit behavior before actual fabrication happens, potentially saving significant re-design costs. The simulation of a circuit critically depends on the so-called compact models and therefore:

• The accuracy of the compact-model equations
• The quality of the model parameters

Compact models predict the device terminal characteristics by means of computationally inexpensive equations. With increasingly advanced technologies, compact models have been growing significantly in complexity. At the same time an increasingly diverse set of technologies is offered to designers, requiring specific compact models for each kind of electron device.
The complexity of compact models has made the manual integration into simulators a tedious, error-prone and therefore expensive task. One reason for this is that not only the model equations have to be implemented, but also their symbolic derivatives. Numeric derivatives are not an option because they are orders of magnitude slower to compute than analytical derivatives and can introduce convergence problems due to inaccuracies. It is not uncommon - even in commercial tools - to find model implementation bugs or to observe convergence problems that result from incorrectly implemented derivatives. Some simulators with no or limited Verilog-A integration do not implement certain compact-models and can therefore not be used to simulate some processes at all.
Manually implemented compact models may differ between simulators since EDA vendors often rename parameters or alter particular model equations. Due to these simulator specific peculiarities, PDKs can usually only be used by a few specific simulators.

Verilog-A has been developed to address these problems and has become the de-facto standard for developing and distributing compact models. It allows implementing compact models via a simulator independent and standardized language. Verilog-A compilers can translate these models to machine code and allow simulators to use these models without manually implementing them. Verilog-A enables:

• model development and customization by allowing to quickly modify the model equations without having to worry about model implementation details.
• implementing behavioral or data-driven models, or even entire circuits.
• inherent portability between simulators for both models and PDKs that would not be possible with traditional netlist-based formats.

Model development and customization is necessary for advanced technologies and applications, for example quantum computing, where existing models cannot provide satisfactory results and must be adjusted. It also enables research and development.

[read more at <https://openvaf.semimod.de/>]

[paper] BioDynaMo: a modular platform for high-performance agent-based simulation

Lukas Breitwieser^1,2, Ahmad Hesam^1,3, Jean de Montigny¹, Vasileios Vavourakis^4,5, Alexandros Iosif⁴, Jack Jennings⁶, Marcus Kaiser^6,7,8, Marco Manca⁹, Alberto Di Meglio¹, Zaid Al-Ars³, Fons Rademakers¹, Onur Mutlu², Roman Bauer¹⁰

BioDynaMo: a modular platform for high-performance agent-based simulation

Bioinformatics on 21 September 2021

DOI: 10.1093/bioinformatics/btab649/6371176 

  
1 CERN openlab, CERN, European Organization for Nuclear Research, Geneva, Switzerland
2 ETH Zurich, Swiss Federal Institute of Technology in Zurich, Zurich, Switzerland
3 Delft University of Technology, Delft, The Netherlands
4 Department of Mechanical & Manufacturing Engineering, University of Cyprus, Nicosia, Cyprus
5 Department of Medical Physics & Biomedical Engineering, University College London, UK
6 School of Computing, Newcastle University, Newcastle upon Tyne, UK
7 Department of Functional Neurosurgery, Ruijin Hospital, Shanghai Jiao Tong University School of Medicine, Shanghai, China
8 Precision Imaging Beacon, School of Medicine, University of Nottingham, UK
9 SCimPulse Foundation, Geleen, Netherlands
10 Department of Computer Science, University of Surrey, Guildford, UK

Abstract: Agent-based modeling is an indispensable tool for studying complex biological systems. However, existing simulation platforms do not always take full advantage of modern hardware and often have a field-specific software design.

Results: We present a novel simulation platform called BioDynaMo that alleviates both of these problems. BioDynaMo features a modular and high-performance simulation engine. We demonstrate that BioDynaMo can be used to simulate use cases in: neuroscience, oncology, and epidemiology. For each use case we validate our findings with experimental data or an analytical solution. Our performance results show that BioDynaMo performs up to three orders of magnitude faster than the state-of-the-art baselines. This improvement makes it feasible to simulate each use case with one billion agents on a single server, showcasing the potential BioDynaMo has for computational biology research.

Availability: BioDynaMo is an open-source project under the Apache 2.0 license and is available at www.biodynamo.org. Instructions to reproduce the results are available in supplementary information.

Fig: BioDynaMo’s layered architecture. BioDynaMo is predominantly executed on multi-core CPUs, is able to offload computations to the GPU, and supports Linux operating systems. BioDynaMo provides a rich set of low- and high-level features commonly required in agent-based models. On top of these generic features, BioDynaMo offers model building blocks to simplify the development of a simulation. Even if BioDynaMo does not provide the required building blocks, users still benefit from all generic agent-based features (illustrated by the vertical extension of the “Simulation" layer).

Acknowledgments: We want to thank Giovanni De Toni for his work on the BioDynaMo build system. This work was supported by the CERN Knowledge Transfer office [to L.B. and A.H.]; the Israeli Innovation Authority [to A.H.]; the Research Excellence Academy from the Faculty of Medical Science of the Newcastle University [to J.dM.]; the UCY StartUp Grant scheme [to V.V.]; the Medical Research Council of the United Kingdom [MR/N015037/1 to R.B., MR/T004347/1 to M.K.]; the Engineering and Physical Sciences Research Council of the UK [EP/S001433/1 to R.B., NS/A000026/1, EP/N031962/1 to M.K.]; a PhD studentship funded by Newcastle University’s School of Computing [to J.J.]; the Wellcome Trust [102037 to M.K.]; the Guangci Professorship Program of Ruijin Hospital (Shanghai Jiao Tong Univ.) [to M.K.]; and by several donations by SAFARI Research Group’s industrial partners including Huawei, Intel, Microsoft, and VMware [to O.M.]. The authors have declared that no competing interests exist.

[paper] eSim: An Open Source EDA Tool

Rahul Paknikar, Saurabh Bansode, Gloria Nandihal, Madhav P. Desai, Kannan M. Moudgalya, 

and Ashutosh Jha*

eSim: An Open Source EDA Tool for Mixed-Signal and Microcontroller Simulations

4th International Conference on Circuits, Systems and Simulation

(ICCSS), 2021, pp. 212-217,

DOI: 10.1109/ICCSS51193.2021.9464198.

Indian Institute of Technology Bombay, Mumbai, Maharashtra, India
* Vellore Institute of Technology Chennai, Tamil Nadu, India

Abstract: The ability to carry out simulations before making a PCB can save a lot of time, effort and cost. This work explains the creation of an open source mixed-signal simulation software eSim that will be of great help to students, hobbyists, the SME sector and startups. Analog and digital components are respectively modelled using SPICE and a hardware descriptive language in eSim. Inclusion of AVR based microcontroller as a part of the digital circuit is demonstrated through its instructions implemented as a C code library. This methodology could be used to provide support to other microcontroller families, such as PIC, STM and also more sophisticated controllers. These concepts are demonstrated through a few examples.

Fig: Workflow of NGHDL

Acknowledgment: The authors would like to thank Prof. Pramod Murali, Department of Electrical Engineering, IIT Bombay and Mrs. Usha Viswanathan, FOSSEE, IIT Bombay for their guidance. We would also like to express our gratitude towards Powai Labs Technology Private Limited for their gratis contribution to the VHPIDIRECT package and Utility package of NGHDL. The FOSSEE project is funded by the National Mission on Education through ICT, Ministry of Education, Govt. of India.

[paper] NESS Open-Source TCAD Environment

Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Ali Rezaei, Daniel Nagy,

Vihar P. Georgiev, and Asen Asenov

Nano-Electronic Simulation Software (NESS): 

A Novel Open-Source TCAD Simulation Environment

Journal of Microelectronic Manufacturing

Vol 3 (4) : 20030407 2020

DOI:  10.33079/jomm.20030407

Abstract: This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software (NESS) which is currently under development at the Device Modeling Group of the University of Glasgow. NESS is designed with the main aim to provide an open, flexible, and easy to use simulation environment where users are able not only to perform numerical simulations but also to develop and implement new simulation methods and models. Currently, NESS is organized into two main components: the structure generator and a collection of different numerical solvers; which are linked to supporting components such as an effective mass extractor and materials database. This paper gives a brief overview of each of the components by describing their main capabilities, structure, and theory behind each one of them. Moreover, to illustrate the capabilities of each component, here we have given examples considering various device structures, architectures, materials, etc. at multiple simulation conditions. We expect that NESS will prove to be a great tool for both conventional as well as exploratory device research programs and projects.

Fig: Randomly generated atomistic device considering random discrete dopants (RDD) and metal gate granularity (MGG) in the NESS simulation domain

Acknowledgments: This project was initiated by the European Union Horizon 2020 research and innovation programme under grant agreement No. 688101 SUPERAID7 and has received further funding from EPSRC UKRI Innovation Fellowship scheme under grant agreement No. EP/S001131/1 (QSEE), No. EP/P009972/1 (QUANTDEVMOD) and No. EP/S000259/1 (Variability PDK for design based research on FPGA/neuro computing); and from H2020-FETOPEN-2019 scheme under grant agreement No.862539-Electromed-FET OPEN. The coauthors would like to thank Dr. Carrillo-Nuñez, Dr. Lee, Dr. Berrada, Dr. Badami, and Dr. Duan for their former contribution to NESS; as well as Dr. Donetti for the possibility of using the 1DMC tool. 

[paper] Vertical Graphene–hBCN Heterostructure TFETs

A comparative computational study of tunneling transistors

based on vertical graphene–hBCN heterostructures

Mahsa Ebrahimi¹, Ashkan Horri¹, Majid Sanaeepur², and Mohammad Bagher Tavakoli¹

J. Appl. Phys. 127, 084504 (2020); DOI: 10.1063/1.5130777

Published Online: 28 February 2020

¹Department of Electrical Engineering, Arak Branch, Islamic Azad University, Arak, Iran
²Department of Electrical Engineering, Faculty of Engineering, Arak, Iran

ABSTRACT In this paper, the electrical characteristics of tunneling transistors based on vertical graphene and a hexagonal boron-carbon-nitrogen (hBCN) heterostructure are studied and compared theoretically. We have considered three different types of hBCN, i.e., BC₂N, BC₂N₀, and BC₆N as a tunneling barrier. Our simulation is based on the nonequilibrium Green’s function formalism along with an atomistic tightbinding (TB) model. The TB parameters are obtained by fitting the band structure to first-principles results. By using this method, electrical characteristics of the device, such as the ION=IOFF ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. For a fair comparison, the effects of geometrical variations and number of tunneling barrier layers on the electrical parameters of the device are simulated and investigated. We show that, by an appropriate design, the device can be used for low-power or high-performance applications. The device allows current modulation exceeding 106 at room temperature for a 0.6 V bias voltage.

FIG. DFT Band structure for (a) graphene - hBC₂N₀ - graphene (b) graphene - hBC₂N - graphene and (c) graphene - hBC₆N - graphene supercell. BC and BV represent barrier height in the conduction band and valence band, respectively, all simulated with QUANTUM ESPRESSO: A modular and opensource software for quantum simulations of materials