CMOS-SOI-MEMS Uncooled Infrared Security Sensor With Integrated Readout https://t.co/FRVIoqutaL #papers #feedly

CMOS-SOI-MEMS Uncooled Infrared Security Sensor With Integrated Readout https://t.co/FRVIoqutaL #papers #feedly

— Wladek Grabinski (@wladek60) April 29, 2016

from Twitter https://twitter.com/wladek60

April 29, 2016 at 10:37PM
via IFTTT

Realizing Efficient Volume Depletion in SOI Junctionless FETs https://t.co/F3sOQxVV30 #papers #feedly

Realizing Efficient Volume Depletion in SOI Junctionless FETs https://t.co/F3sOQxVV30 #papers #feedly

— Wladek Grabinski (@wladek60) April 29, 2016

from Twitter https://twitter.com/wladek60

April 29, 2016 at 09:52PM
via IFTTT

Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers

Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers

— Wladek Grabinski (@wladek60) April 27, 2016

from Twitter https://twitter.com/wladek60

April 27, 2016 at 02:50PM
via IFTTT

Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers

Bipolar Resistive RAM Based on HfO2 : Physics, #Compact #Modeling, and Variability Control https://t.co/DEoGJpqLUA #papers

— Wladek Grabinski (@wladek60) April 27, 2016

from Twitter https://twitter.com/wladek60

April 27, 2016 at 02:50PM
via IFTTT

5 Eclipse tools for processing and visualizing data https://t.co/XNd6R5dQW3 #papers

5 Eclipse tools for processing and visualizing data https://t.co/XNd6R5dQW3 #papers

— Wladek Grabinski (@wladek60) April 25, 2016

from Twitter https://twitter.com/wladek60

April 25, 2016 at 08:56PM
via IFTTT

Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs https://t.co/3hTmr2Kwmv #papers #papers

Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs https://t.co/3hTmr2Kwmv #papers #papers

— Wladek Grabinski (@wladek60) April 23, 2016

from Twitter https://twitter.com/wladek60

April 23, 2016 at 01:33PM
via IFTTT

III–V Tunnel FET Model With Closed-Form Analytical Solution https://t.co/mExcthY64C #papers #feedly #papers

III–V Tunnel FET Model With Closed-Form Analytical Solution https://t.co/mExcthY64C #papers #feedly #papers

— Wladek Grabinski (@wladek60) April 23, 2016

from Twitter https://twitter.com/wladek60

April 23, 2016 at 01:27PM
via IFTTT

#Compact #Model for MetalOxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers

#Compact #Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers

— Wladek Grabinski (@wladek60) April 22, 2016

from Twitter https://twitter.com/wladek60

April 22, 2016 at 05:53PM
via IFTTT

Physically Based Compact Mobility Model for Organic Thin-Film Transistor https://t.co/2iRX20ogJL #papers

Physically Based Compact Mobility Model for Organic Thin-Film Transistor https://t.co/2iRX20ogJL #papers

— Wladek Grabinski (@wladek60) April 22, 2016

from Twitter https://twitter.com/wladek60

April 22, 2016 at 06:39PM
via IFTTT

#Compact #Model for MetalOxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers

#Compact #Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification https://t.co/DhlMo2ZenF #papers

— Wladek Grabinski (@wladek60) April 22, 2016

from Twitter https://twitter.com/wladek60

April 22, 2016 at 05:53PM
via IFTTT

SPICE models for Precision DACs https://t.co/evOjXzJZYd #papers

SPICE models for Precision DACs https://t.co/evOjXzJZYd #papers

— Wladek Grabinski (@wladek60) April 21, 2016

from Twitter https://twitter.com/wladek60

April 21, 2016 at 08:20PM
via IFTTT

[mos-ak] A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis

A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis  

M. E. Brinson 1,* andV. Kuznetsov 2  

Keywords:Qucs; Verilog-A analogue module synthesis;equation-defined devices (EDD); compact device modelling; circuit simulation  

Summary: Since the introduction of SPICE non-linear controlled voltage and current sources, they have become a central feature in the interactive development of behavioural device models and circuit macromodels. The current generation of SPICE-based open source general public license circuit simulators, including Qucs, Ngspice and Xyce©, implements a range of mathematical operators and functions for modelling physical phenomena and system performance. The Qucs equation-defined device is an extension of the SPICE style non-linear B type controlled source which adds dynamic charge properties to behavioural sources, allowing for example, voltage and current dependent capacitance to be easily modelled. Following, the standardization of Verilog-A, it has become a preferred hardware description language where analogue models are written in a netlist format combined with more general computer programming features for sequencing and controlling model operation. In traditional circuit simulation, the generation of a Verilog-A model from a schematic, with embedded non-linear behavioural sources, is not automatic but is normally undertaken manually. This paper introduces a new approach to the generation of Verilog-A compact device models from Qucs circuit schematics using a purpose built analogue module synthesizer. To illustrate the properties and use of the Qucs Verilog-A module synthesiser, the text includes a number of semiconductor device modelling examples and in some cases compares their simulation performance with conventional behavioural device models. Copyright © 2016 John Wiley & Sons, Ltd.  

Article first published online: 15 APR 2016; DOI: 10.1002/jnm.2166  

References
[1] Newton AR, Pederson DO, Sangiovanni-Vincentelli A. SPICE Version 2g User's Guide. Department of Electrical Engineering and Computer Sciences, University of California: Berkeley, CA, 1981.
Go here for SFX
[2] Johnson B, Quarles T, Newton AR, Pederson DO, Sangiovanni-Vincentelli A. Berkeley, CA. Department of Electrical Engineering and Computer Sciences, University of California, 1992.
Go here for SFX
[3] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs (Quite universal circuit simulator), 2015. Available from: http;//qucs.sourceforge.net [Accessed November 2015].
[4] Nenzi P, Vogt H. Ngspice-26 (Next generation SPICE version 26), 2015. Available from: http://ngspice.sourceforge. net. [Accessed November 2015].
[5] Sandia National Laboratories, US, Xyce parallel electronic simulator version 6.3., 2015. Available from: http: //xyce.sandia.gov.[Accessed November 2015].
[6] Jahn S, Brinson ME. Interactive compact device modelling using Qucs equation-defined devices. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2008; 21(5): 335–349.
Direct Link:
Abstract PDF(1011K) References Web of Science® Times Cited: 7 Go here for SFX
[7] Brinson ME, Jahn S. Qucs: a GPL software package for circuit simulation, compact device modelling and circuit macromodelling from DC to RF and beyond. International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2009; 22(4): 297–319.
Direct Link:
Abstract PDF(1156K) References Web of Science® Times Cited: 7 Go here for SFX
[8] Accellera, Verilog-AMS Language Reference Manual. Version 2.3.1., 2009. Available from: http://www.accellera.org. [Accessed November 2015.]
[9] Silicon Integration Initiative (Si2), Compact Model Coalition, 2015. Available from: http;//www.si2.org. [Accessed November 2015.]
[10] Brinson ME, Jahn S. Modelling high-frequency inductance with Qucs non-linear radio frequency equation defined devices.International Journal of Electronics 2009; 96(3): 307–321.
CrossRef, Web of Science® Times Cited: 1
Go here for SFX
[11] Lemaitre L, Gu B. ADMS - A fully Customizable Compact Model Compiler, NSTI-Nanotech, 2008. Available from: www.nsti.org[Accessed March 2016].
Go here for SFX
[12] Lemaitre L, Grabinski W, McAndrew C. Compact device modelling using Verilog-AMS and AMS. Electron Technology (Internet Journal). June 6 2003, pp 1-5. Available from: http://www.ite.waw.pl/etij/pdf/35-03p.pdf. [Accessed November 2015.]
[13] Lemaitre L, McAndrew CM, Hamm S. Automatic Device Model Synthesis. CICC: Florida, USA, 2002.
Go here for SFX
[14] Eaton JW. GNU Octave. Version 4.0, 2015. Available from: https:www.gnu.org/software/octave/. [Accessed November 2015.]
[15] Brinson M, Crozier R, Novak C, Roucaries B, Schreuder F, Torri GT. Building a second generation Qucs GPL circuit simulator: package structure, simulation features and compact device modelling capabilities. London, 2014. Available from: http://www.mos-ak.org/london−2014/presentations/09−Mike−Brinson−MOS-AK−London−2014.pdf. [Accessed November 2015].
Go here for SFX
[16] Brinson M, Crozier R, Kuznetsov V, Novak C, Roucaries B, Schreuder F, Torri GT. Qucs: an introduction to the new simulation and compact device modelling features implemented in release 0.0.19/0.0.19Src2 of the popular GPL circuit simulator. MOS-AK ESSDERC/ESSCIRC Workshop. 18 September Graz, Austria 2015. Available from: http://www.mos-ak.org/graz−2015/presentationsT−5−Brinson−MOS-AK−Graz−2015.pdf. [Accessed November 2015].
Go here for SFX
[17] Anognetti P, Massobrio G. Semiconductor Device Modeling with SPICE. McGraw-Hill Inc: New York, 1988.
Go here for SFX
--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

CMC Leadership

CMC Leadership represents the industry’s top semiconductor design companies and manufacturers.

In their role, they provide overall direction and guidance to the efforts of the members and the developers involved in CMC working groups.

Chair: Dr. Peter Lee, Micron Technology

Vice-Chair: Dr. Josef Watts, GLOBALFOUNDRIES

Secretary Richard Williams, IBM

Treasurer: Takeshi Naito, Toshiba

[read more...]

A review of electrical characterization techniques for ultrathin FDSOI materials and devices https://t.co/TCICVWiFdW #papers #feedly

A review of electrical characterization techniques for ultrathin FDSOI materials and devices https://t.co/TCICVWiFdW #papers #feedly

— Wladek Grabinski (@wladek60) April 15, 2016

from Twitter https://twitter.com/wladek60

April 15, 2016 at 10:13PM
via IFTTT

A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis https://t.co/IsNSKkSLtL #papers

A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis https://t.co/IsNSKkSLtL #papers

— Wladek Grabinski (@wladek60) April 15, 2016

from Twitter https://twitter.com/wladek60

April 15, 2016 at 10:12PM
via IFTTT

Characterization and modeling of drain current local variability in 28 and 14nm FDSOI nMOSFETs https://t.co/3bOVSMHjON #papers

Characterization and modeling of drain current local variability in 28 and 14nm FDSOI nMOSFETs https://t.co/3bOVSMHjON #papers

— Wladek Grabinski (@wladek60) April 14, 2016

from Twitter https://twitter.com/wladek60

April 14, 2016 at 10:30PM
via IFTTT

[mos-ak] [press note] Spring MOS-AK Workshop @ cfaed

The MOS-AK Association held its annual spring compact modeling and Verilog-A standardization workshop at the Center for Advancing Electronics Dresden (cfaed), TU Dresden, on March 18, 2016

Published on Tue, 05 Apr 2016 in MARTIN CLAUS GROUP <https://cfaed.tu-dresden.de/claus-group/news_reader/spring-mos-ak-workshop-cfaed>

More than 40 registered academic researchers and modeling engineers attended two sessions to hear 10 technical compact modeling engineering talks. This year, compact modeling of emerging technologies such as organic transistors, carbon nanotube transistors and chemical transistors were in focus with contributions from industry and academia. "The talks and discussions revealed an increasing interest of industry and system designers to evaluate the performance and applicability of emerging technologies," summarized cfaed group leader Dr.-Ing. Martin Claus, local organizer of the workshop in Dresden. He pointed out that "compact models bridge the gap between technology development and applications by providing useful insights for guiding the technology development and by enabling circuit design." MOS-AK is a dedicated forum for engineers and scientists working in that field. The MOS-AK Dresden workshop presentations are available here: http://www.mos-ak.org/dresden_2016/

The event received full sponsorship from leading industrial partners as well as technical program promotion by the cfaed, IEEE WIE Swiss Chapter, IEEE EDS German Chapter, NEEDS Nanohub as well as Europractice.

The MOS-AK Association is coordinating several upcoming modeling events focusing on the Verilog-A compact model standardization as well as open source FOSS TCAD/EDA simulation tool developments: 

Future MOS-AK workshops

• Shanghai
• Lausanne

IEEE EDS Mini-Colloquium on CM

• April 9, 2016 IIT Roorkee (IN)

MIXDES Compact Modeling Session

• June 23-25, 2016 Lodz (PL)

IEEE EDS Mini-Colloquium on GaN HEMT

• June 22, 2016, prior MIXDES 2016 Conference

4th Training Course on CM (TCCM)

• June 27-28, 2016 Tarragona (SP)

In the meantime, please also visit www.mos-ak.org where the discussions of all compact/SPICE modeling topics and its Verilog-A standardization will be continued.

About MOS-AK Association: The MOS-AK is a HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware compact/SPICE models and its Verilog-A standardization. The MOS-AK workshops play a central role in developing a common modeling interface among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact model standardization and related tools for model development, validation and its implementation and distribution.

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Special Issue #papers: Planar Fully-Depleted SOI technology https://t.co/kuUWaIigqx

Special Issue #papers: Planar Fully-Depleted SOI technology https://t.co/kuUWaIigqx

— Wladek Grabinski (@wladek60) April 14, 2016

from Twitter https://twitter.com/wladek60

April 14, 2016 at 10:29AM
via IFTTT

25th Anniversary of the World Wide Web conference - Journal of Web Semantics - Elsevier https://t.co/qAZK9S2qXJ #papers

25th Anniversary of the World Wide Web conference - Journal of Web Semantics - Elsevier https://t.co/qAZK9S2qXJ #papers

— Wladek Grabinski (@wladek60) April 13, 2016

from Twitter https://twitter.com/wladek60

April 13, 2016 at 12:45PM
via IFTTT

[mos-ak] [2nd Announcement and Call for Papers] Summer MOS-AK Workshop Shanghai June 26-28, 2016

 Summer MOS-AK Workshop  

 Shanghai June 26-28, 2016 
  2nd Announcement and Call for Papers  

Together with the MOS-AK Honorary Committee represented by Profs. Tzu-Yin Chiu, SMIC and Ming-Kai Tsai, MediaTek SRC/CMC Chair, MOS-AK Workshop Scientific Program Coordinators: George Ponchak, Lingling Sun, Yuhua Cheng, Larry Nagel and Andrei Vladimirescu, local workshop organizer Min Zhang, SIMTAC (Shanghai) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held at SIMTAC in Shanghai between June 26-28, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:

Call for Papers - March. 2016
2nd Announcement - April 2016
Final Workshop Program - May 2016
International MOS-AK Workshop:

June 26 - MOS-AK Training Course

June 27 - 1st Day Workshop

June 28 - 2nd Day Workshop

Venue:

SIMIT/SIMTAC

Shanghai (CN)

Topics to be covered include the following among other related to the compact/SPICE modeling :

• Advances in semiconductor technologies and processing
• Compact Modeling (CM) of the electron devices
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC Designs
• Foundry/Fabless Interface Strategies
  

Speakers: tentative list of MOS-AK Experts:

• Franz Sischka, SisConsult, (D)
  
• Mostafa Emam, Incize (B)
  
• Paulius Sakalas, CEDIC, TUD, (D)
  
• Thomas Gneiting AdMOS (D)
  
• Wladek Grabinski, MOS-AK (EU)
  
• Bertrand Ardouin, XMOD (F)
  
• Zhiping Yu, Stanford University (USA)
  
• Lining Zhang, HKUST (HK)
  

Online MOS-AK Abstract Submission:
Authors should submit an abstract using on-line MOS-AK submission:

http://www.mos-ak.org/shanghai_2016/

(any related inquiries can be sent to abstracts@mos-ak.org)

Online Workshop Registration:

http://www.mos-ak.org/shanghai_2016/
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

MNE&MS 2016: Seminar Announcement

MNE&MS 2016

Seminar Announcement

The 8th traditional seminar “Computer simulation and design of micro-and nanoelectronics and micro-electromechanical systems” (MNE&MS 2016), organized by the Nanotechnology Center “OrelNano” and Physics Department will take place at the Orel State University after Ivan Turgenev, 29 Naugorskoe Shosse (in 212 Auditorium), Orel, Russia, on April 29th 2016 from 10am to 5pm.

The main objective of the MNE&MS 2016 is to allow regional electronics industry companies and Universities present results in research and development in micro-and nanoelectronics, power electronics, and microelectromechanical systems (MEMS) to potential customers, interested professionals, and students. Hence, the scope of seminar covers the most of Key Enabling Technologies (KETs), that is the basis for innovations in a range of products across all industrial sectors.

The Seminar also aims to introduce to Companies and Universities the latest developments in the electronics development automation (EDA), in particular in technology computer aided design (TCAD) and in compact modeling. Seminar includes session with oral presentations, poster session and an Exhibition of products of participating companies.

Selected papers will be recommended for publication in journals “Fundamental and Applied Problems of Technics and Technology” and “Information Systems and Technologies”. In addition, selected papers will be recommended for publication in proceedings of “Nanosystems, nanomaterials and nanotechnologies” of the XIV International Scientific Practical Internet – Conference “Energy and Resource Saving – XXI Century”. Information about previous regional seminars is available online.

Will be coffee breaks during seminar. In campus there is students diner and hotel (Naugorskoe Shosse 29 A). On April 30, Saturday, Organizing Committee can organize trip to the Spasskoye-Lutovinovo - State Memorial and Natural Reserve Museum of famous Russian writer Ivan Turgenev.

Our University located in South-West of Central Russia in historical town Orel (or Oryol), that was founded in 1566. Orel placed on Oka and Orlik rivers junction in 382 km from Moscow and has beautiful surroundings with number of historical landmarks.

Contact phones: +79208250040
Hotel reception phone is +7(4862)419882 or +79038816347
Official language of seminar – Russian.
There is no registration fee.

[Incize] Senior Semiconductor R&D Engineer

Incize is recruiting a senior semiconductor R&D engineer for a three-year research project. The project aims to develop an innovative semiconductor characterization technique that is of great interest for the semiconductor industry.

What Incize offers:

• Permanent contract
• Infinite opportunities to learn
• Friendly and flexible environment
• Competitive salary

What Incize requires:

• PhD in physics, electronics or material science
• Knowledge of semiconductor physics, microwave theory, optics and their applications
• Experience  in  designing  and  running  experiments  in  microwave  and  optics domains
• Experience in TCAD and ADS simulations
• Clean-room experience is an advantage
• Passion for research and innovation
• 2-3 years of experience in R&D after PhD

Your Responsibilities

• Development of a new characterization method and its theoretical background
• Planning and execution of experiments
• Numerical TCAD and ADS simulations
• Literature search

How to apply

Please send your CV, a list of publications and a cover letter to info@incize.com with the subject line job_RD01_2016_lastname. References should be provided upon request.

About Incize

Incize provides characterization and modelling services for semiconductor foundries and fabless companies. It is a spin-off from Université catholique de Louvain and is based in Louvain-la-Neuve, Belgium. Visit www.incize.com to find out more.

www.incize.com

Chemin du Cyclotron, 6

B-1348 Louvain-la-Neuve, Belgium

T: +32 10 39 22 60

F: +32 10 39 20 01