Old glories never die... do they?

It's quite hard for an old glory like HSPICE to die. See the post in aboutSpice.com:
SMIC Deploys Synopsys HSPICE Simulator for 45-nm Physical IP and Standard Cell Development (Synopsys)

Have a nice summertim

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An Insider’s View to the Swiss LP/LV CMOS Design History

Organizers: Jean-Michel Sallese; EPFL and Wladek Grabinski; GMC Consulting
Host: Predrag Habas; EM Marin

Where: EPFL - Swiss Federal Institute of Technology, Lausanne, Room CO017
When: Friday, July 3, 2009, 5:00 pm

Title: An Insider’s View to the Swiss LP/LV CMOS Design History
Presenter: Stefan Cserveny

Abstract: I worked the last 30 years at CEH - CSEM, the amazing Swiss crucible at the origin of the very low power integrated circuits, taking advantage of its highly professional, creative and enthusiastic teams and the close and fruitful collaboration with the EPFL and the Swiss industry. I will present some of these historical developments as viewed by the subjects in which I had the opportunity to add my contribution. After a short overview of my background and work done before joining the CEH, I will first present the early compact MOS modeling work done in order to satisfy the requirements for the LP/LV design including the near threshold range - a work setting the path towards the presently largely used EKV model. The following items are some of the sensor interface circuits, the realization of embedded low power non-volatile memories and, finally, the very low leakage SRAM memories essential for many critical applications.

Short Bio: Stefan Cserveny is retiring after 47 years of teaching and research and development activities as an electron device engineer and as a circuit designer, especially for designs requiring device expertise. The first 17 years he lectured electron devices and circuits at the Polytechnic Institute of Bucharest, Romania and at the Telecommunication Institute of Oran, Algeria, which he helped to create, writing several textbooks and scientific papers. In 1972 he obtained a one year specialization grant he spent at the University of California Berkeley where he received the M.S. degree in electrical engineering. In 1979 he joined the 17 years old CEH, which in 1984 became part of CSEM, getting involved with the LP/LV challenge first needed for the watch industry. In his position of scientific expert he contributed to research projects and ASIC developments; most interesting results have been published. He also participated in the BCTM technical program committee, reviewed a large number of papers and did consulting for Swiss companies.

QUCS developments

The QUCS development team is taking part in the MOS Modelling and Extraction Working Group (MOS-AK) Verilog-A standardisation initiative.

Read more...

The QUCS Team is also contributing to the MIXDES special session "Device Level Support for Emerging CMOS Technologies" organised by Daniel Tomaszewski; ITE, Poland and Wladek Grabiński; GMC Suisse (with MOS-AK/GSA Group and COMON EU Project coordination)

Read the QUCS paper's abstract: "Compact Device Modeling for Established and Emerging Technologies with the Qucs GPL Circuit Simulator"

Future Solutions of System On Chip (SoC)

Frédéric Boeuf, Principal Engineer at STM, gave a short course at the VLSI Symposium 2009 in Kyoto. It is a synthesis on the silicon technology uses for system on chip applications, and some prospect about the future solutions.

View the slide presentation...

IMEC Tips 10 nm Options at Tech Forum

I copy a post from Semiconductor International:
IMEC Tips 10 nm Options at Tech Forum: "At the IMEC Technology Forum in Brussels, Belgium, IMEC Fellow Marc Heyns presented various CMOS transistor possibilities for 15 nm and beyond. "We are at the brink of a new era of innovation," Heyns said, adding that he sees no fundamental barriers to scaling to the 10 nm node. One roadmap involves the integration of new materials and structures over time..."
(read more)

MNE'09 in Ghent

The 35th International Conference on Micro & Nano Engineering (MNE), to be held in Ghent, Belgium from 28 September to 1 October 2009.

The scope is about micro- and nano-fabrication and manufacturing using lithography and other nano-patterning related approaches. The conference brings together engineers and scientists from all over the world to discuss recent progress and future trends in the fabrication, manufacturing and application of micro-and nano-structures and devices. Applications in electronics, electromechanics, environment and life sciences are discussed such as: nanoelectronics, MEMS-NEMS, bioMEMS and lab-on-a-chip devices.

Read more...

International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation

The Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation will be held at the University College London (UCL) in London (UK) on September 25 2009.

This workshop is intended to provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in collaboration with IEEE UCL-Cambridge University EDS/LEOS Chapter joint chapter that is in the process of formation. Topics include include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

The deadline for Abstract Submission is July 15 2009.

Prospective authors should submit a 500-word abstract to: m.bauza@ucl.ac.uk

If their abstract is accepted, the authors will be invited to submit of a 4-page paper to be included in proceedings. The deadline is August 15, 2009.

This is the only workshop especifically devoted to the compact modeling of TFT!

Compact modeling postdoc position at Institute of Electron Technology (Warsaw, Poland)

The Division of Silicon Microsystem and Nanostructure (http://www.ite.waw.pl/en/Z02.php) at Institute of Electron Technology (http://www.ite.waw.pl/en/index.php), Warsaw, Poland is seeking an experienced researcher for a position in the frame of a European Marie Curie Project.

Area of work
The researcher will work in the area of compact modelling of multi-gate MOSFETs. Two main topics should be covered during the researcher stay in ITE:
- development of parameter extraction methods for multi-gate MOS devices, using I-V, C-V, G-V characteristics of sets of devices, and based on combination of global optimization (constrained or unconstrained) and local fitting approaches,
- development of parameter extraction methods based on electrical characteristics of sets of multi-gate MOS devices, which account for parameters fluctuations within a wafer; (example: extraction of MOSFETs size variations DW, DL due to systematic and/or statistic photolithography and other processes fluctuations).

The work will be done in collaboration with a leading European semiconductor foundry, and leading modelling and characterization groups from European universities.

Contract details
Temporary contract, duration 20 months, full time, starting date 1 October 2009. This postdoc post is funded by the Marie-Curie European Compact Modelling network. The net monthly salary is more than 2200 Euro/month.

Application deadline: 31 August 2009.

Contact: Dr. Daniel Tomaszewski, email: dtomasz@ite.waw.pl

Requirements
Candidates should possess either
- a Ph.D. degree or
- a M.Sc. or Dipl.-Ing. Degree and at least 4 years of research experience
in electrical engineering, preferably in semiconductor microelectronics.

Good skills in written and spoken English are mandatory.

Desirable is research experience in the following areas:
- Compact modeling of MOS devices
- Characterization methods of MOS devices
- Numerical simulation of MOS devices
- Numerical methods
- Programming

Compact Modeling Job Vacancy at Technical University Ilmenau, Germany

The RF & Nano Device group (http://www.tu-ilmenau.de/fakei/1342+M54099f70862.0.html) at TU Ilmenau (http://www.tu-ilmenau.de/uni/index.php) is seeking an experienced researcher for a position in the frame of a European Marie Curie Project.

The researcher will work on compact modeling of high-frequency transistors, in
particular HEMTs (High Electron Mobility Transistor). He or she will be responsible
for the development of compact models for the large-signal high-frequency behavior of
HEMTs. This will include models for the dc current-voltage characteristics and the high-frequency large-signal behavior of HEMTs with special emphasis on the modeling of nonlinearities including the extraction of model parameters from experimental results. The work will be done in close contact to a leading European semiconductor foundry.

Contract details: Temporary contract, duration 20 months, full time, starting date 1 September 2009.

Application deadline: 31 July 2009.

Contact: PD Dr. Frank Schwierz, email: frank.schwierz@tu-ilmenau.de

Requirements: Candidates should possess either

- a Ph.D. degree or

- a Master or Dipl.-Ing. Degree and at least 4 years of research experience

in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.

Desirable is research experience in the following areas:

- Compact modeling of semiconductor devices

- Large-signal modeling and analysis

- Nonlinear behavior of semiconductor devices and modeling of nonlinearities.

IEEE SCV EDS Electron Device talks for June

"Negative Bias Temperature Instability in p-MOSFETs: Fundamentals, Characterization, Materials Dependence and Modeling"
Speaker: Dr. Souvik Mahapatra, Dept. of Electrical Engineering, IIT Bombay
Date: Tuesday, June. 9, 2009
Location: National Semiconductor, Building E1, Conference Center, 2900 Semiconductor Drive, Santa Clara, CA 95051.

More information at the IEEE Santa Clara Valley EDS Chapter Home Page.

Job offers

Three nice job offers:

Microwave Device Modeling Engineer, Massachusetts
Device Modeling Engineer, Cambridgeshire
Device Simulation Engineer - Solar, Surrey

Remember that we only post these offers here as an act of good will, and we're not related in any form to any of them...