[paper] Analog System Synthesis for Reconfigurable Computing

Afolabi Ige, Linhao Yang, Hang Yang, Jennifer Hasler, and Cong Hao

Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing

J. Low Power Electron. Appl. 2023, 13, 58. 

DOI: 10.3390/jlpea1304005

* Electrical and Computer Engineering (ECE), Georgia Institute of Technology (USA)

Abstract: The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.

Figure: The analog synthesis tool flow to generate a design on a large-scale Field Programmable Analog Array (FPAA) or an Application-Specific Integrated Circuit (ASIC). A single user-supplied high-level description goes through multiple lowering steps to reach the targeted output, either GDSII or a switch list. For targeting an FPAA, a design can either be specified through the GUI in XCOS (a pre-existing flow) or through the new text-based Python flow. Users construct circuits and systems using class objects provided in the Python cell library that mirror the palette browser in the XCOS library, and the description is then lowered into a Verilog syntax. The FPAA path lowers to Blif netlist, fitting into our preexisting flow compiling a switch list to target the FPAA. For targeting an ASIC, users perform similar steps to construct a system from Python objects with cells made available in the provided library. Those Python objects are then converted to a Verilog netlist before being fed to the layout synthesis modules, which handle placement and global routing. These serve as inputs to the open-source detailed router (TritonRoute) to convert the guide to a path. That path is merged with the placement file to create a final output layout file.

Funding: Partial funding for the development of this effort came from NSF (2212179).

[paper] DEVSIM

Sanchez, J. E.,

DEVSIM: A TCAD Semiconductor Device Simulator

Journal of Open Source Software, 7(70), 3898, (2022).

DOI:10.21105/joss.03898

Abstract: DEVSIM is technology computer-aided design (TCAD) software for semiconductor device simulation. By solving the equations for electric fields and current flow, it simulates the electrical behavior of semiconductor devices, such as transistors. It can be used to model existing, fabricated devices for calibration purposes. It is also possible to explore novel device structures and exotic materials, reducing the number of costly and time-consuming manufacturing iterations While DEVSIM has limited capabilities for the creation of 1-D and 2-D meshes, the Pythoninterface allows the import of mesh structures from any format using a triangular representation (in 2-D) or a tetrahedral representation (in 3-D). This makes it possible for the user to utilize high quality open source meshing solutions.

FIG: 90-nm 3-D MOSFET. The polysilicon gate (2) is surrounded by oxide (5) and two nitride regions (3) and (4). The bulk region (1) has a 120nm drawn gate length. The source and drain contacts are both 50 nm underneath the nitride regions. A body contact was placed on the bottom of the 60nm silicon region. The oxide thickness is 4.9 nm and the device is 25nm thick.

[paper] STT-MTJ Device Model

Haoyan Liu and Takashi Ohsawa
General-Purpose STT-MTJ Device Model Based on the Fokker-Planck Equation
IEEE Transactions On Nanotechnology, VOL. 22, 2023 659 A
DOI: 10.1109/TNANO.2023.3322468.

Graduate School of Information, Production and Systems, Waseda University (J)

Abstract: A thermally agitated device model of spin-transfer torque magnetic tunnel junction (STT-MTJ) based on the Fokker-Planck equation is proposed which is implemented into HSPICE by using Verilog-A. We compared different techniques of finite difference method (FDM) and analyzed the impact of the solvers on computational efficiency and accuracy. A framework is proposed which traces dynamics of a particular STT-MTJ’s angle between the magnetic moments of the free and the pinned layers and makes the model applicable to a wide range of circuits. The model was applied to the 4T2MTJ memory cell array and a leaky integrate and-fire (LIF) neuron circuit to validate the stochastic switching characteristic and the angle prediction function. In the memory array simulations, the CPU time consumption for this model is 1/30 of the model which is based on the stochastic Landau-Lifshitz Gilbert-Slonczewski equation.

Fig: (a) Structure of 1T1MTJ synapse. (b) Binary weights in 10 neurons and an input digit ‘9’ of spiking neural network (surrounded by the dotted square) used for the experiment shown. Each digit is a 28×28 matrix. Each figure shows two output spikes fired in the neurons representing ‘0-9’. The total spike numbers of the neurons which represent 0-9 are 2, 3, 4, 3, 4, 4, 4, 4, 4 and 9. 

Acknowledgement: This work was supported in part by Synopsys Corporation, in part by JSPS KAKENHI under Grant JP20K04626, in part by VLSI Design and Education Center (VDEC), University of Tokyo with collaboration with Cadence Corporation, and in part by the cooperation of organization between Kioxia Corporation and Waseda University.

[chapter] Extraction for a 65nm FG Transistor.

[chapter] Cong, T.D., Hoang, T. (2023). A Methodology of Extraction DC Model for a 65 nm Floating-Gate Transistor. 

In: Dao, NN., Thinh, T.N., Nguyen, N.T. (eds) Intelligence of Things: Technologies and Applications. ICIT 2023. Lecture Notes on Data Engineering and Communications Technologies, vol 187. Springer, Cham. https://doi.org/10.1007/978-3-031-46573-4_19

Abstract: Floating-gate Metal-Oxide Semiconductor (MOS) has been investigated and applied in many applications such as artificial intelligence, analog mixed-signal, neural networks, and memory fields. This study aims to propose a methodology for extracting a DC model for a 65 nm floating-gate MOS transistor. The method in this work uses the combination architecture of MOS transistor, capacitance, and voltage-controlled voltage source which can archive a high accuracy result. Moreover, the advantage of the method is that the MOS transistor was a completed model which enhances the flexibility and accuracy between a fabricated device and modeled architecture. In our work, the industrial standard model Berkeley Short-channel IGFET Model (BSIM) 3v3.1, level 49 was deployed, and the DC simulation was obtained with the use of LTspice tool.

[book] Microelectronic Circuits

Sedra, Adel S., Smith, Kenneth Carless, Carusone, 

Tony Chan, Gaudet, Vincent. 

Microelectronic Circuits. 

United Kingdom: Oxford University Press, 2020

Circuits by Sedra and Smith has served generations of electrical and computer engineering students as the best and most widely-used text for this required course. Respected equally as a textbook and reference, "Sedra/Smith" combines a thorough presentation of fundamentals with an introduction to present-day IC technology. It remains the best text for helping students progress from circuit analysis to circuit design, developing design skills and insights that are essential to successful practice in the field. Significantly revised with the input of two new coauthors, slimmed down, and updated with the latest innovations, Microelectronic Circuits, Eighth Edition, remains the gold standard in providing the most comprehensive, flexible, accurate, and design-oriented treatment of electronic circuits available today.

Appendix

• B. SPICE Device Models and Design with Simulation Examples

Model files for representative CMOS technologies are provided below:

• 0.8 um CMOS
• 0.35 um CMOS
• 0.18 um CMOS
• 45 nm CMOS
• 7nm FinFET

 

[paper] Sub-THz HICUM for SiGe HBTs

Soumya Ranjan Panda, Thomas Zimmer, Anjan Chakravorty, Nicolas Derrier

and Sebastien Fregonese

Exploring Compact Modeling of SiGe HBTs in Sub-THz Range With HICUM

in IEEE TED, DOI: 10.1109/TED.2023.3321017.

IMS laboratory, CNRS, University of Bordeaux (F)
Department of Electrical Engineering, IIT Madras (IN)
STMicroelectronics, 38920 Crolles (F)

Abstract : This study delves deeper into the high frequency (HF) behavior of state-of-the-art sub-THz silicon germanium heterojunction bipolar transistors (SiGe HBTs) fabricated with 55 nm BiCMOS process technology from STM. Using measurement data, calibrated TCAD simulations, and compact model simulations, we present a comprehensive methodology for extracting several HF parameters (related to parasitic capacitance partitioning and nonquasi-static effects) of the industry standard model, HICUM. The parameter extraction strategies involve thorough physics-based investigation and sensitivity analysis. The latter allowed us to precisely evaluate the effects of parameter variations on frequency dependent characteristics. The accuracy of the finally deployed model is tested by comparing the model simulation with measured small-signal two-port parameters of SiGe HBTs up to 330 GHz.

FIG: a.)  TEM image of the SiGe HBT device; b.) 2D TCAD structure simulation; c.) Large signal equivalent circuit of HICUM L2 compact model; d.) and e.) adjunct networks for vertical NQS effects

Acknowledgment: The authors would like to acknowledge Dider Celi, STM, for valuable discussion about the compact modeling of heterojunction bipolar transistors (HBTs), and they also like to thank STM for providing the silicon wafers. This work was supported by NANO2022 Important Project of Common European Interest Project (IPCEI), and SHIFT Grant ID 101096256.

[paper] Lorentzian noise spectra in compact models

Nikolaos Makris*†, Loukas Chevas* and Matthias Bucher*

Verilog-A based implementation of Lorentzian noise spectra in compact models

26th International Conference on Noise and Fluctuations - ICNF

17th-20th October 2023 - Grenoble - France

DOI: 10.1109/ICNF57520.2023.10472771

* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece        European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece

Abstract:In this paper, a simple Verilog-A implementation of Lorentzian noise spectra is introduced that can be used in compact models for the frequency-domain simulation of low-frequency noise in electronic devices. For this purpose, a thermal noise source is combined with a low-pass filter as realized using laplace_nd Verilog-A function in order to achieve Lorentzian noise behavior. This modeling approach can be implemented in any Verilog-A compact model and provides the means for bias-dependent Lorentzian trap modeling. This approach is evaluated in commercial simulator. Application examples are provided to demonstrate the capabilities of this approach.

FIG: Bias dependent model implemented in the EKV3 MOSFET model

Acknowledgements: This work was co-funded by the ERASMUS+ Programme of the European Union (Contract number: 101004049 - EURECA-PRO - EAC-A02-2019 / EAC-A02-2019-1). This research has been co-financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH - CREATE - INNOVATE (project code: T2EDK-00340).

[mos-ak] [2nd Announcement] 16th International MOS-AK Workshop Silicon Valley, Dec. 13, 2023

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

16th International MOS-AK Workshop

Silicon Valley, December 13, 2023

2nd Announcement and C4P

The 16th International MOS-AK Workshop on Compact/SPICE Modeling will take place on Dec.13, 2023, in timeframe of IEDM and Q4 CMC Meetings. This event is coorganized by Keysight Technologies, our local host and partner, and the Extended MOS-AK TPC Committee. We invite you to join us for MOS-AK workshop and learn from the experts in the field of SPICE/Verilog-A modeling.

Planned 16th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, Organic TFT, CMOS and SOI-based memory
• Microwave, RF device modeling, high voltage device modeling
• Device level modeling for Agroelectronics, Bio/Med, IoT applications
• Device cryogenic operation for Quantum Computing 
  
• Nanoscale semiconductor devices/circuits and its reliability/ageing
• Technology R&D, DFY, DFT and IC Designs
• Foundry/Fabless Interface Strategies, Open Access PDK(eg: Skywater 130nm CMOS, IHP 130nm RF BiCMOS) 

Online Abstract Submission is open (any related enquiries can be sent to abstracts@mos-ak.org)

Online Free Registration is open (any related enquiries can be sent to registration@mos-ak.org)

Important Dates: 

• 2nd Announcement: Oct. 20213
  
• Final Workshop Program: Nov.28 2023
• MOS-AK Workshop: Dec.13, 2023
  in timeframe of IEDM and Q4 CMC Meetings

W.Grabinski for Extended MOS-AK Committee

WG171023

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[Call for Book Chapters] Perovskite Solar Cells

Call for Book Chapters:

Book Title: Perovskite Solar Cell

Table of Content

• Introduction to Perovskite Solar Cells
• Fundamentals of Perovskite Materials
• Fabrication Techniques
• Characterization Methods
• Perovskite Solar Cell Physics

Important Dates:

Chapter proposal submission deadline: 15th November 2023
Notification of Acceptance: 21st November 2023
Full Chapter submission: 30th January 2024
Acceptance/Rejection Notification: 10th February 2024

Prospective authors are requested to submit their chapter proposals/full chapters. 

<https://www.routledge.com/our-customers/authors/publishing-guidelines>

There are no publication fees for a chapter submitted to this book publication. All submitted chapters will be peer reviewed. For chapter proposals/full chapter submission and queries: tdsubash2007@gmail.com

[webinar] IEEE SCV-EDS: Investigating quantum speed limits with superconducting qubits

The Electron Devices Society Santa Clara Valley/San Francisco joint Chapter is hosting Prof. Meenakshi Singh. The title of the lecture is ‘Investigating quantum speed limits with superconducting qubits’

When: Friday, Oct. 20, 2023 – 9am to 10am (PDT)
Where: This is an online event and attendees can participate via Zoom.

Registration or Send an email to hiuyung.wong at ieee.org to get the zoom link indicating if you are IEEE member, IEEE EDS member, IEEE Student member

Abstract: The speed at which quantum entanglement between qubits with short range interactions can be generated is limited by the Lieb-Robinson bound. Introducing longer range interactions relaxes this bound and entanglement can be generated at a faster rate. The speed limit for this has been analytically found only for a two-qubit system under the assumption of negligible single qubit gate time. We seek to demonstrate this speed limit experimentally using two superconducting transmon qubits. Moreover, we aim to measure the increase in this speed limit induced by introducing additional qubits (coupled with the first two). Since the speed up grows with additional entangled qubits, it is expected to increase as the system size increases. This has important implications for large-scale quantum computing.

Speaker Bio: Dr. Singh is an experimental physicist with research focused on quantum thermal effects and quantum computing. She graduated from the Indian Institute of Technology with an M. S. in Physics in 2006 and received a Ph. D. in Physics from the Pennsylvania State University in 2012. Her Ph. D. thesis was focused on quantum transport in nanowires. She went on to work at Sandia National Laboratories on Quantum Computing as a post-doctoral scholar. She is currently an Associate Professor in the Department of Physics at the Colorado School of Mines. At Mines, her research projects include measurements of spin-orbit coupling in novel materials and thermal effects in superconducting hybrids. She recently received the NSF CAREER award to pursue research in phonon interactions with spin qubits in silicon quantum dots.

[IHP Career] Research associate for Open PDK Development

Research associate for Open PDK Development (m/f/d)

Developer for Open Source Process Design Kits for SiGe-BiCMOS technolog

Job-ID: 7064/23 | Department: Technology | Salary: as per tariff TV-L | Working time: 40h/week (part-time work option) | Limitation: initially 2 years with option of extension | Entry Date: as soon as possible

The position:

As a member of the group Research & Prototyping Service you will develop Process Design Kit (PDK) for IHP’s BiCMOS technologies and new future technology modules. Your detailed tasks will include programming (e.g. pcells or run decks for DRC and LVS) for commercial as well as open-source tools for ASIC design environments.

Devices descriptions, user guides and test cases are important aspects of your work, too. Implementation of new devices and investigations into new design tools and flows, this includes adaption of tools, will give this position room interesting development opportunities.

Your profile:

You hold a Master's degree in computer science with strong background in semiconductors, physics or electrical engineering. Knowledge in semiconductor devices and programming are of advantage. Your specialized knowledge preferably covers ASIC design environment like Cadence Virtuoso, Mentor/Siemens/Tanner, KeySight ADS or the open source tools like OpenROAD/OpenLane.

Furthermore, you have skills for programming in scripting languages (e.g. Python, Perl or TCL). You are well organized and always keep the overview even with many parallel projects. Thanks to your skillful communication, you are a binding and reliable contact person for our partners.

You are also a strong team player. We are looking for a team member, who is able to structure his or her own work and to bring a well-organized and systematic way of working into the cooperation with creative minds. You are an ideal match for this position, when you have experimental, analytical and problem-solving skills, very strong communicative skills and the ability to quickly learn how to operate the latest technical equipment including various software. It is necessary that you confidently handle the English language. Knowledge of the German language is welcome.

The consolidating of German language skills is expected and highly encouraged, for example in in-house language courses and intensive courses.

Further Information Online Application Form

[conference] FIRST 2023

Website: http://sme.tju.edu.cn/info/1095/2265.htm

English: https://www.aconf.org/conf_194081.html

Date: 30 Oct 2023 (Mon) to 31 Oct 2023 (Tue)

Main Organizer: Tianjin University

Venue: Online

Theme: Interdisciplinarity: The Fusion of Technologies (Semiconductor, Artificial Intelligence, Internet-of-Things, and Communications)

The inaugural FIRST international conference will be held online on Monday, 30th and Tuesday 31st October 2023. Many world-renowned professors, experts and researchers in communication and semiconductor technologies and other related fields at home and abroad will attend this conference. This international conference aims to discuss the open problems and present new solutions that address the challenges of future communication systems, artificial intelligence, internet-of-things, and chip design. Specifically, the role of semiconductors in future communications will be presented and how can the semiconductor and communication industry emerge stronger after the pandemic will be discussed.

This FIRST international conference will be open to relevant enterprises and experts in the field of semiconductors and integrated circuits, providing a professional multi-disciplinary and multi-field exchange and cooperation platform for enterprises, universities and research institutes in the field of semiconductors and integrated circuits, providing innovative ideas for today's increasingly complex and difficult product development, combining cutting-edge scientific research and product innovation more effectively. At the same time, it lays a solid foundation for more in-depth school-enterprise cooperation.

Registration（注册网址）: 中文站 - https://www.aconf.cn/conf_194081.html

[C4P] IJNM - 7th Sino MOS-AK Workshop

Call for Papers

Special issue on the 7th International Sino MOS-AK Workshop

Submission deadline: Sunday, 31 December 2023

The 7th International Sino MOS-AK Workshop was held on 11-13th August 2023 in Nanjing, China. MOS-AK working group has more than 20 years enabling  compact modeling  R&D exchange. For additional detailed info, please refer to MOS-AK website:
http://www.mos-ak.org/nanjing_2023/.

With the aggressive scaling of CMOS technologies and constantly emerging diversified devices, accurate device modeling technique poses severe challenge to circuit and system designers, in particular for RF/MW/mmW/THz/Power/optics. With this background, the workshop aims to strengthen a network and discussion forum among experts in the field, provide a forum for the presentation and discussion of the leading-edge research and development results of Analytical Modeling, Compact Modeling, Characterization and Simulation techniques for advanced devices, circuits and technologies. Modeling and validation technique of all solid-state devices, including, Si, III-V, power, nanoscale electronic structures and other related new devices are within the scope of the conference. The theme of MOS-AK is "Bridge of Process Technology and Integrated Circuits & Systems Design".

Topics for this call for papers include but not restricted to:

• Advances in semiconductor technologies and processing (CMOS, SOI, FINFET, III-V, Wide band-gap)
• CM of passive active, sensors, and actuators
• Emerging Devices, photonic devices, CMOS, and SOI-based memory cell
• RF/THz device and Power device modeling
• Power device and Power integration
• Reliability modeling
• AI and machine learning in EDA & modeling application
• Nanoscale CMOS devices and circuits
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open-source TCAD/EDA modeling and simulation
• Technology R&D, DFY, DFT and IC Designs
• Chiplet Modeling and Packaging-related modeling
• Foundry/Fabless Interface Strategies, Open Access PDKs
• DTCO & STCO-related EDA tools/technologies
• Other related topics

Guest Editors:

• Jun Zhang
  Nanjing University of Posts and Telecommunications (CN)
• Yuehang Xu
  University of Electronic Science and Technology of China (CN)
• Wladek Grabinski
  MOS-AK (EU)

Submission Guidelines/Instructions

Authors of papers presented at the conference will be invited to submit an extended paper by 31 December 2023 to a special issue of IJNM. Manuscripts for this special issue should adhere to the requirements for regular papers in IJNM as specified in the journal’s Author Guidelines. The manuscripts will be submitted via the IJNM manuscript submission site, https://wiley.atyponrex.com/journal/jnm. Authors must choose the special issue title from the dropdown list on the “Additional Information” tab.

SUBMIT NOW

[book chapters] Equation-Based Compact Modeling

 

Debnath, P., Sarkar, B., & Chanda, M. (Eds.). (2023).

Differential Equation Based Solutions 

for Emerging Real-Time Problems

(1st ed.). CRC Press 

DOI 10.1201/9781003227847

Chapter: Differential Equation-Based Compact 2-D Modeling of Asymmetric Gate Oxide Heterojunction Tunnel FET; By: Sudipta Ghosh, Arghyadeep Sarkar

Abstract: Tunnel Field Effect Transistor (TFET) has emerged as an effective alternative device to replace MOSFET for a few decades. The major drawbacks of MOSFET devices are the short-channel effects, due to which the leakage current increases with a decrease in device dimension. So, scaling down TFET is more efficacious than that of MOSFETs. Sub-threshold swing (SS) is another advantageous characteristic of TFET devices for high-speed digital applications. In TFETs the SS could be well below 60 mV/decade, which is the thermal limit for MOSFET devices and therefore makes it more suitable than MOSFET for faster switching applications. It is observed from the literature studies that the performances of the TFET devices have been explored thoroughly by using 2-D TCAD simulation but an analytical model is always essential to understand the physical behavior of the device and the physics behind this; which facilitates further, the analysis of the device performances at circuit level as and when implemented.

Chapter: Differential Equation-Based Analytical Modeling of the Characteristics Parameters of the Junctionless MOSFET-Based Label-Free Biosensors; by: Manash Chanda, Papiya Debnath, Avtar Singh

Abstract: Recently Field Effect transistor (FET)-based biosensing applications have gained significant attention due to the demand for quick and accurate diagnosis of different enzymes, proteins, DNA, viruses, etc; cost-effective fabrication process; portability and better sensitivity and selectivity compared to the existing biosensors. FET is basically a three-terminal device with source, drain, and gate terminals. Basically, the gate terminal controls the current flow between the source and drain terminals. In FETs, first, a nanogap is created in the oxide layer or in the gate by etching adequate materials. When the biomolecules are trapped inside the nanocavity then the surface potentials change and also the threshold voltage varies. As a result, the output current also changes. Finally, by measuring the changes in the threshold voltage or the device current, one can easily detect the biomolecules easily.

[open positions] TU Warsaw

 

We [TU Warsaw] offer two #openpositions for PhDs who perform research in the broad field of technology, characterization, and modeling of #semiconductor structures and devices. The first position is for a #postdoctoralfellowship, while the second one is for an #assistantprofessor. The specifics of both offers are attached to this post. The candidates will be employed in the Institute of Microelectronics and Optoelectronics, Faculty of Electronics and Information Technologies of Warsaw University of Technology. Both positions will start in December 2023/January 2024.

Links to offers with a list of documents to apply:

• (PostDoc): https://lnkd.in/di7dwV5p
• (Assistant Professor): https://lnkd.in/dk5d6Dfa

Interested applicants should contact Robert Mroczyński with a complete professional CV (including educational background, experience, and a list of publications), an electronic version (pdf) of the Ph.D. thesis, and the contact information to at least two experts who would provide letters of recommendation.

[Short Course] MACHINE LEARNING FOR ELECTRON DEVICES

Short Course on

MACHINE LEARNING FOR ELECTRON DEVICES

3-6 October 2023, IIT Roorkee

Four day residential program to learn and explore the role of Machine Learning in shaping the future of the semiconductor EDA.

KEY HIGHLIGHTS

• Lectures from basic machine learning to advanced ideas
• Hands-on tutorials for developing your own Machine learning models
• Excellent networking opportunity
• Interaction with experts from industry and academia
• UG Fellowships up to ₹ 10000/month for selected participants
• Funding opportunity upto INR 40Lacs as start-up seed grant for selected ideas

EVENT SCHEDULE <http://ece.iitr.ac.in/diraclab/mled23/>

[paper] GaN-on-Si HEMT

Rijo Baby^a, Manish Mandal^b, Shamibrota K. Roy^b, Abheek Bardhan^a, Rangarajan Muralidharan^a, Kaushik Basu^b, Srinivasan Raghavan^a, Digbijoy N. Nath^a

8A, 200V normally-off cascode GaN-on-Si HEMT: From epitaxy to double pulse testing

Microelectronic Engineering, Volume 282, 2023, 112085,

DOI: 10.1016/j.mee.2023.112085.

a Center for Nanoscience and Engineering (CeNSE), (IISc Bangalore (IN)
b Department of Electrical Engineering, IISc Bangalore (IN)

Abstract: In this paper, we provide a comprehensive study on all aspects of development of normally-off multi-finger III-nitride HEMT on Silicon in cascode configuration. AlGaN/GaN HEMT epi-stack with in situ SiN cap was grown on 2" Silicon (111) using MOCVD, utilizing a 2-step AlN nucleation, step-graded AlGaN transition layer and C-doped GaN buffer. Depletion-mode HEMTs in winding gate geometry with a gate width of 30mm were fabricated with thick electroplated metal contacts and an optimized bilayer SiN passivation. Devices were diced and packaged in TO254 with conducting epoxy and Au-coated ceramic substrate. These packaged D-mode HEMTs exhibited a threshold voltage (Vth) of −12V, maximum ON current of 10A and a 3-terminal hard breakdown in excess of 400V. Bare dies of D-mode HEMTs were then integrated with commercially procured silicon MOSFET in a TO254 package in cascode configuration to achieve Vth>2V, ON current of 8Aand breakdown >200V. The normally-off cascaded GaN HEMTs were subjected to various gate and drain stress measurements and were found to exhibit a Vth shift of 10 mV after 1000 s of positive gate (+5V) stress. The input and output capacitances of the cascode devices were measured to be 1 nF and 0.8 nF, respectively. The 3rd quadrant operation was checked at 8 A on-state current level to reveal a lower voltage drop of 0. V. Finally, cascode HEMTs were subjected to double pulsed testing (DPT) using a half-bridge evaluation board. On and off rise times of 52 ns and 59 ns were obtained along with energy loss of 25 μJ and 20 μJ, respectively, for devices switched at 8A,100V.

FIG: 8A, 200 V normally-off cascode GaN-on-Si HEMT

Acknowledgement: This research was supported by ISRO/SCL. We also acknowledge funding support from MHRD through the NIEIN project, from MeitY and DST Nano Mission through NNetRA. We thank the Micro and Nano Characterization Facility (MNCF) staff and facility technologists of the National Nano Fabrication Facility (NNFC). We thank Anirudh Venugopalarao, Parimalazhagan Serralan, Mr. Veera Pandi N, Dr. M.M Nayak, Mr. Malingu G and Bharath Kumar M for their support.

[paper] Knowing Your Heart Condition Anytime

Lei Wang, Xingwei Wang, Dalin Zhang, Xiaolei Ma, Yong Zhang, Haipeng Dai, 

Chenren Xu, Zhijun Li, Tao Gu

Knowing Your Heart Condition Anytime:

User-Independent ECG Measurement Using Commercial Mobile Phones

Proceedings of the ACM on Interactive, Mobile, Wearable and Ubiquitous Technologies

Vol. 7, Issue 3, Article No.: 131, pp 1–28

DOI: 10.1145/3610871

Abstract: Electrocardiogram (ECG) monitoring has been widely explored in detecting and diagnosing cardiovascular diseases due to its accuracy, simplicity, and sensitivity. However, medical- or commercial-grade ECG monitoring devices can be costly for people who want to monitor their ECG on a daily basis. These devices typically require several electrodes to be attached to the human body which is inconvenient for continuous monitoring. To enable low-cost measurement of ECG signals with off-the-shelf devices on a daily basis, in this paper, we propose a novel ECG sensing system that uses acceleration data collected from a smartphone. Our system offers several advantages over previous systems, including low cost, ease of use, location and user independence, and high accuracy. We design a two-tiered denoising process, comprising SWT and Soft-Thresholding, to effectively eliminate interference caused by respiration, body, and hand movements. Finally, we develop a multi-level deep learning recovery model to achieve efficient, real-time and user-independent ECG measurement on commercial mobile phones. We conduct extensive experiments with 30 participants (with nearly 36,000 heartbeat samples) under a user-independent scenario. The average errors of the PR interval, QRS interval, QT interval, and RR interval are 12.02 ms, 16.9 ms, 16.64 ms, and 1.84 ms, respectively. As a case study, we also demonstrate the strong capability of our system in signal recovery for patients with common heart diseases, including tachycardia, bradycardia, arrhythmia, unstable angina, and myocardial infarction.

Fig:  Seismocardiogram (SCG) ECG recovery system:

(a) Typical application scenario with SCG/ECG system 

(b) Interface of the mobile APP.

Acknowledgments: This research is supported by National Natural Science Foundation of China (Grant No. 62102006). This work is also in part supported by The Natural Science Foundation of the Jiangsu Higher Education Institutions of China (Grant No. 1020231697)

[C4P] LASCAS 2024

 

LASCAS 2024

An IEEE CASS Flagship Conference

15th IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS

February 27 - March 01, 2024

ieee-lascas.org

PUNTA DEL ESTE - URUGUAY

Since its first edition in 2010, LASCAS provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. This event is a space where the CAS community can present new concepts and innovative approaches, learn about new trends and solutions, and receive feedback from specialists in diverse fields.

The 15th edition will take place in Punta del Este, Uruguay. With its lush landscapes, pristine beaches, and sophisticated amenities, it has established itself as a premier tourist destination in South America. It offers an unparalleled experience, where visitors can immerse themselves in a rich blend of natural beauty and modern luxury. The city is easily accessible by air, with regular flights from major cities in South America, and just 90 minute from Montevideo and its international airport. Punta del Este is ready to receive you. The symposium will cover technical novelties and tutorial overviews on circuits and systems topics including but not limited to:

● Analog and Digital Signal Processing

● Biomedical Circuits and Systems

● Intelligent Sensor Systems and Internet of Things

● Artificial Intelligence and Smart Systems

● Nanoelectronics and Gigascale Systems

● Electronic Design Automation

● Circuits and Systems for Communications

● RF Circuits and Systems

● Smart Systems and Smart Manufacturing

● Power Systems and Power Electronic Circuits

● Multimedia Systems and Applications

● Life Science Systems and Applications

● Electronic Testing

● Fault Tolerant Circuits

● Nonlinear Circuits and Systems

● Cognitive Computing and Deep Learning

● Computing and Big Data Applications

Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. Best papers will be invited to a special edition of the IEEE Transactions on Circuits and Systems I (TCAS-I) and IEEE Transactions on Circuits and Systems II (TCAS-II). A social program will be offered, including special events and tours to selected attractions for the attendees and their guests.

General Chairs:

Dr. Matías Miguez – UCU, Uruguay. 

Dr. Pablo Pérez-Nicoli – Udelar, Uruguay. 

Program Chairs:

Dr. Maysam Ghovanloo –Silicon Creations, USA

Dr. José Lipovetzky – IB-CNA, Argentina